Title Page
Contents
Abbreviations 12
ABSTRACT 13
Chapter 1. Introduction 15
1.1. Background 15
1.2. Necessity and Significance of SFCC Study 17
1.2.1. Necessity of SFCC Study 17
1.2.2. Significance of SFCC Study 18
1.3. Scope and Objectives of the Dissertation 19
1.3.1. Research Scope 19
1.3.2. Research Objectives 19
Chapter 2. Theoretical Concept of SFCC Employing a Full-bridge Circuit and an HTS DC Reactor 20
2.1. Introduction to SFCC 20
2.2. Configuration of SFCC System 27
2.3. Fault Current Control Scheme of SFCC 29
Chapter 3. Development of the prototype 40V /30 A class SFCC 34
3.1. HTS DC Reactor 34
3.1.1. Superconducting Wire 35
3.1.2. Fabrication of HTS DC Reactor 38
3.1.3. RMC Bias Method 46
3.2. Embedded Control Unit for Fault Current Control 52
3.2.1. Concept of Embedded Control Unit 52
3.2.2. HIL Simulation 54
3.2.3. Main Algorithm of Embedded Control Unit 57
3.2.4. Implementation of Embedded Control Unit Based on HIL Simulation 64
3.3. Fabrication of 40 V /30 A class SFCC System 68
3.3.1. HTS DC Reactor 70
3.3.2. Embedded Control Unit 72
3.3.3. Gate Pulse Generating Circuit 72
3.3.4. Thyristors and Diodes 75
Chapter 4. Feasibility Tests and Experimental Result Analysis of SFCC 77
4.1. Experimental Setup of SFCC Short Circuit Test 77
4.1.1. Short Circuit Test Environment 77
4.1.2. Short Circuit Test Apparatuses 79
4.2. Result Analysis of Short Circuit Test 84
4.2.1. Effect of SFCC on Fault Current Limitation 84
4.2.2. Fault Current Control Tests 87
4.3. Discussion for SFCC System 90
Chapter 5. Application Studies of SFCC to AC Electric Power System 91
5.1. The Problem Caused by Fault Current in Synchronous Generator of Power System 91
5.2. Stability Analysis of Synchronous Generator System Employing SFCC 92
5.2.1. Concept of Power System Stability 92
5.2.2. Calculation of Transient Stability 93
5.2.3. Transient Stability Improvement through SFCC 100
Chapter 6. Conclusion 107
References 110
국문요약 116
Table 3.1. Parameters of pancake type HTS DC reactor through simulations. 42
Table 3.2. Specifications of SuNAM CC tape. 45
Table 3.3. Specifications of pancake coil for RMC bias feasibility test. 49
Table 3.4. Parameters of short circuit test. 50
Table 3.5. Calculated phase angle with respect to line impedance at 30 V/ 40 A class SFCC system 61
Table 3.6. Specifications of embedded control unit. 72
Table 3.7. Specifications of thyristor and diode. 75
Table 4.1. Experimental condition of short circuit test whose object is to verify the effect of SFCC. 84
Table 4.2. Experimental condition of fault current control tests. 87
Table 5.1. Power system simulation model specifications. 102
Fig. 2.1. Power grid branch composed of CB, fuse and SFCC. 22
Fig. 2.2. Operating points on the TCC curve. 23
Fig. 2.3. Schematic drawing showing the concept of single phase SFCC system. 25
Fig. 2.4. Flow chart of the control procedure of SFCC. 26
Fig. 2.5. Structure of developed SFCC. 28
Fig. 2.6. Current path of SFCC 29
Fig. 2.7. Current waveform at normal state. 30
Fig. 2.8. Peak fault current with respect to phase angle. 33
Fig. 3.1. Critical surface of a superconductor. 35
Fig. 3.2. Architecture of 1G and 2G wire. 37
Fig. 3.3. First peak current values with respect to HTS DC reactor inductance. 39
Fig. 3.4. Schematics of pancake type and solenoid type coils. 40
Fig. 3.5. The dependence of critical current of the superconducting tape on the perpendicular magnetic field. 43
Fig. 3.6. Perpendicular magnetic field analysis. 44
Fig. 3.7. Structure of SuNAM CC tape. 45
Fig. 3.8. Fabricated HTS DC reactor. 46
Fig. 3.9. Bias point moving by RMC. 47
Fig. 3.10. Three test models 48
Fig. 3.11. Photograph of an air core HTS pancake coil(left) and iron core with permanent magnets (right). 49
Fig. 3.12. Short circuit scheme. 50
Fig. 3.13. Short circuit test results with respect to DC reactor type. 51
Fig. 3.14. Operational process of embedded control unit. 54
Fig. 3.15. Process of HIL simulation. 56
Fig. 3.16. Fault current control process algorithm. 58
Fig. 3.17. Circuit diagram of phase angle data table calculation simulation. 60
Fig. 3.18. Voltage and current waveform for calculation of equivalent short circuit line impedance. 63
Fig. 3.19. Simulink code for phase angle calculation. 65
Fig. 3.20. Line impedance (impedance between the power source ans SFCC) calculation Stateflow block. 66
Fig. 3.21. Schematic diagram of fabricated SFCC system. 69
Fig. 3.22. V-I curve which shows the critical current of HTS DC reactor. 71
Fig. 3.23. Gate pulse generating circuit diagram. 73
Fig. 3.24. Fabricated gate pulse generating circuit. 74
Fig. 3.25. Pulse diagram of TCA 785 device. 76
Fig. 4.1. Schematic circuit diagram for fault current test. 78
Fig. 4.2. AC power supply. 80
Fig. 4.3. Load bank. 80
Fig. 4.4. Fabricated fault switch. 81
Fig. 4.5. Monitoring system of embedded control unit. 82
Fig. 4.6. Picture of short circuit test. 83
Fig. 4.7. Short circuit results 85
Fig. 4.8. Short circuit test results 89
Fig. 5.1. Explanation drawing of step by step method. 98
Fig. 5.2. Simplified power system simulation model. 101
Fig. 5.3. Generated output power of synchronous machine as a function of thyristor phase angle. 103
Fig. 5.4. Flow chart of transient state power angle calculation. 104
Fig. 5.5. Power angle deviation with respect to thyristor phase angle. 105