With the advancement of complementary metal-oxide-semiconductor (CMOS) technology there has been strong demand for higher performance and lower energy consumption of devices. Engineers have been successfully fulfilling this demand mainly with device scaling thus far, but it is becoming increasingly apparent that existing devices are approaching their limits. A great deal of research has consequently been focused on so-called "steep slope transistors", which can reduce both threshold voltage and supply voltage remarkably. The tunnel field-effect transistor (TFET) is considered to be the most promising candidates for a steep slope transistor. Its carrier transport is mainly based on band-to-band tunneling (BTBT). which leads to a subthreshold swing (SS) below the thermionic emission limit of 60 mV/decade.

In conventional p-i-n TFETs, there is a critical problem that the SS value is abruptly degraded as the gate bias increases, which results in low on current. Because the gate electric field decreases as the distance from the surface increases, this causes spatial variation of the tunnel barrier width in the channel depth direction along the source-channel junction, which eventually leads to degradation of the SS. Another issue that determines the performance of the conventional TFET is a doping profile. Since the tunneling barrier width sensitively varies depending on the doping steepness, achieving the abrupt junction between the source and channel is essential. However, device fabrication using high temperature process is not easy to get a sharp doping profile due to the diffusion of dopant atoms.

In this study, we propose a germanium TFET with an electron-hole bilayer (EHB) induced by double gates that are symmetrically arranged and independent biased. By arranging the double gates symmetrically, we establish a simple and feasible structure for an EHBTFET built on a Ge FinFET. Simulation of the proposed device shows a high on/off current ratio of ~ 108 and an extremely low average subthreshold swing of ~ 10mV/dec at VDD＝0.5V. The symmetric gate scheme is possible by using lightly doped drain-source (LDD) structure, which brings the results of low leakage current and minimizing the area loss. Since tunneling probability of the EHBTFET is less sensitive to the doping profile, the device does not require complex fabrication process technique for obtaining the abrupt junction between the source and channel.