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ABSTRACT

목차

제1장 Introduction 10

1.1. Overview 10

1.1.1. High-k/Metal Gate Transistor 10

1.1.2. Non-planar 3D Transistors 11

1.1.3. Transistor Channel Materials 12

1.1.4. New Devices 12

1.2. Objectives of Research 12

1.3. Thesis Organization 13

제2장 Tunnel Field Effect Transistor 14

2.1. Fundamental Limit of Scaling MOSFET 15

2.2. Principles of Operation of the TFET 17

2.3. The WKB approximation 18

2.4. The Subthreshold Regime in the TFET 20

2.5. Challenges of the TFET 21

2.5.1. Tunneling Probability 21

2.5.2. Subthreshold Swing 21

2.5.3. Doping profile 21

2.5.4. Ambipolar Behavior 22

2.6. Development of the TFET 22

제3장 Germanium Electron-Hole Bilayer TFET 24

3.1. Motivation 24

3.2. Structure and Methodology 24

3.2.1. Structure and Operation 24

3.2.2. Substrate Material 26

3.2.3. Fabrication Method 26

3.3. Simulation Approach 28

3.3.1. Parameters 28

3.3.2. Model 29

제4장 Results and Discussion 32

4.1. Operation of the Ge EHBTFET 32

4.2. Electrical Characteristics 33

4.3. Turn-on Voltage Adjustment 36

4.4. Device Optimization 38

4.5. Short Channel Effect 40

4.6. Discussion 41

제5장 Conclusion 45

참고문헌 46

이력서 50

표목차

Table 3.1. Parametrs of simulated EHBTFET 28

그림목차

Figure 1.1. Energy-Efficient Performance Built on Moore's Law. 10

Figure 1.2. Trend in state-of-the art high performance CMOS transistor innovation. 11

Figure 1.3. Evolution of the Field Effect Transistor(FET) architecture. 12

Figure 2.1. Device schematic and band diagram in the on/off-states of the n-channel TFET. 14

Figure 2.2. Qualitative comparison of the characteristics of MOSFET and TFET. 14

Figure 2.3. Transfer characteristics of a MOSFET switch showing an exponential increase in IOFF...[이미지참조] 16

Figure 2.4. Comparison of the minimum switching energy, Emin, and the corresponding voltage supply,...[이미지참조] 17

Figure 2.5. Energy band diagram and layer structure for an nTFET consisting of an n+ source(S), p+...[이미지참조] 18

Figure 2.6. Energy band diagram in the on-state. 18

Figure 2.7. Wavefunctions showing electron tunneling through a rectangular barrier. 19

Figure 2.8. Energy band diagram in the off-state. 22

Figure 2.9. Previeous TFET research and developments. 22

Figure 3.1. Schematic 3D illustration of the EHBTFET with symmetrically arranged and independent... 25

Figure 3.2. Vertical energy band diagrams between gate1 and gate2(a) and cross-section(b) of the EHBT-... 25

Figure 3.3. Process flow for the self-aligned double-gate and fin formation of the EHBTFET. 27

Figure 3.4. Process flow for the poly material double-gate of the EHBTFET. 28

Figure 3.5. Electron density in the same MOS-diode at gate-back voltage VGB＝4V. z is the direction...[이미지참조] 29

Figure 3.6. Drain current ID versus gate-source voltage VGS at 300K and drain-source voltage VDS＝...[이미지참조] 30

Figure 4.1. Vertical energy band diagrams between gate1 (G1) and gate2 (G2) at the on state (VDS＝...[이미지참조] 32

Figure 4.2. Vertical energy band diagrams between gate1 (G1) and gate2 (G2) at the on state (VDS＝...[이미지참조] 33

Figure 4.3. Simulated total current density of the EHBTFET at VDS＝VG1＝0.5V and VG2＝-0.2 V.[이미지참조] 33

Figure 4.4. Simulated (a)transfer and (b)output characteristics of the EHBTFET with gate length of... 34

Figure 4.5. Simulated (a) transfer characteristics and (b) band-to-band tunneling rate of the conventional... 35

Figure 4.6. Simulated transfer characteristics of the (a) conventional TFET and (b) the EHBTFET with... 35

Figure 4.7. At VDS＝VG1＝0.5V, %ION versus steepness.[이미지참조] 36

Figure 4.8. Simulated (a) transfer characteristics and (b)VT variation by VB of the EHBTFET using...[이미지참조] 36

Figure 4.9. Simulated transfer characteristics as a function of VB in log scales.[이미지참조] 37

Figure 4.10. (a) Configuration of hole concentration by VB and (b) simulated 2D hole density distributions...[이미지참조] 37

Figure 4.11. Configuration of carrier concentration at (a)VB 〈〈0V and (b)VB〉〉 0V.[이미지참조] 38

Figure 4.12. Effect of spacer width ranging from 30 ㎚ to 60㎚ at VDS＝0.5V. ION is extracted at...[이미지참조] 39

Figure 4.13. Effect of doping concentration of lightly-doped region (p-, n-) at VDS ＝ 0.5V. ION is...[이미지참조] 39

Figure 4.14. Energy band diagram showing TFET leakage mechanisms in the off-state: direct tunneling... 40

Figure 4.15. The transfer characteristics with gate length variation from 10㎚ to 50㎚: (a) Conventional... 40

Figure 4.16. The ION and ION/IOFF with gate length variation from 10 ㎚ to 50 ㎚ at VDS ＝ 0.5V....[이미지참조] 41

Figure 4.17. Simulated transfer characteristics as a function of channel thickness. 41

Figure 4.18. Energy band diagrams versus the channel thickness. 42

Figure 4.19. Simulated 2D SRH recombination rate and total current density at the off-state. 42

Figure 4.20. VT versus workfunction1 and workfunction2, respectively.[이미지참조] 43

Figure 4.21. Effect of EOT variaion of (a)gate dielectric1 and (b)gate dielectric2 at VDS ＝ 0.5V.[이미지참조] 43

초록보기

With the advancement of complementary metal-oxide-semiconductor (CMOS) technology there has been strong demand for higher performance and lower energy consumption of devices. Engineers have been successfully fulfilling this demand mainly with device scaling thus far, but it is becoming increasingly apparent that existing devices are approaching their limits. A great deal of research has consequently been focused on so-called "steep slope transistors", which can reduce both threshold voltage and supply voltage remarkably. The tunnel field-effect transistor (TFET) is considered to be the most promising candidates for a steep slope transistor. Its carrier transport is mainly based on band-to-band tunneling (BTBT). which leads to a subthreshold swing (SS) below the thermionic emission limit of 60 mV/decade.

In conventional p-i-n TFETs, there is a critical problem that the SS value is abruptly degraded as the gate bias increases, which results in low on current. Because the gate electric field decreases as the distance from the surface increases, this causes spatial variation of the tunnel barrier width in the channel depth direction along the source-channel junction, which eventually leads to degradation of the SS. Another issue that determines the performance of the conventional TFET is a doping profile. Since the tunneling barrier width sensitively varies depending on the doping steepness, achieving the abrupt junction between the source and channel is essential. However, device fabrication using high temperature process is not easy to get a sharp doping profile due to the diffusion of dopant atoms.

In this study, we propose a germanium TFET with an electron-hole bilayer (EHB) induced by double gates that are symmetrically arranged and independent biased. By arranging the double gates symmetrically, we establish a simple and feasible structure for an EHBTFET built on a Ge FinFET. Simulation of the proposed device shows a high on/off current ratio of ~ 108 and an extremely low average subthreshold swing of ~ 10mV/dec at VDD＝0.5V. The symmetric gate scheme is possible by using lightly doped drain-source (LDD) structure, which brings the results of low leakage current and minimizing the area loss. Since tunneling probability of the EHBTFET is less sensitive to the doping profile, the device does not require complex fabrication process technique for obtaining the abrupt junction between the source and channel.

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