Title Page
Contents
Abstract 6
1. Introduction 7
1) Latency 8
2) Low Power Consumption 8
3) Area Optimization 9
2. Related works 10
2.1. Parallel-Based WTA 11
2.2. Binary Tree-based WTA 17
3. Proposed Winner-Take-All Circuit 21
4. Simulation and Comparison Results 26
5. Conclusion 32
References 33
논문요약 35
TABLE 1. Comparison with prior WTA circuit 30
TABLE 2. Comparison with prior WTA circuit at the 28nm process 31
Fig. 1. Principle of the WTA Circuit (a) The structures based on parallel... 10
Fig. 2. High-Speed and High-Precision current WTA circuit 11
Fig. 3. Circuit Diagram of High-Speed and High-Resolution WTA 13
Fig. 4. Voltage-Racing WTA Circuit (a) 4bit linear-delay element circuit... 14
Fig. 5. Waive form of Voltage-Racing WTA (a) Output racing signal (b) Delay... 15
Fig. 6. Low-Power, High-Resolution WTA Circuit Diagram 17
Fig. 7. Low-Power, High-Resolution WTA (a) Pre-Amplifier Circuit (b)... 18
Fig. 8. Circuit architecture of the 10 input WTA 19
Fig. 9. Low-voltage High-Precision Time-Domain WTA 20
Fig. 10. Proposed WTA circuit architecture 21
Fig. 11. Proposed MP_GENERATOR circuit 22
Fig. 12. Waveform of Membrane Potential voltage 23
Fig. 13. Proposed WTA circuit 24
Fig. 14. Proposed WTA physical layout 26
Fig. 15. Proposed WTA circuit simulation waive form 27
Fig. 16. Simulation results of (a) Latency, (b) Power consumption and (c)... 28