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Title page
Contents
Abstract 10
I. Introduction 11
II. Dynamic Load Modulation 13
2.1. Concept of Dynamic Load Modulation 13
2.2. Output Tunable Matching Network 17
2.3. Synthesis of Power Amplifier 19
2.4. Static Measurement 23
III. Digital Pre-distortion 26
3.1. Concept of Digital Pre-distortion 26
3.2. Memory Effect 29
3.3. Procedure of Pre-distortion Algorithm using MATLAB 31
3.4. Verification of Algorithm 35
IV. Measurements 39
4.1. Realization of Measurement Set-up 39
4.2. Time Alignment 42
4.3. Experimental Results 44
V. Conclusion 48
References 49
Table 1. Harmonic load-pull/source-pull results 19
Table 2. Coefficients of polynomial fitting 24
Table 3. Coefficients of PA model used simulation 35
Table 4. Experimental Results of designed RF PA 47
Figure 1. Probability density function of W-CDMA signal 14
Figure 2. Block diagram of dynamic load modulation 15
Figure 3. Modeled junction capacitance of varactor diode 17
Figure 4. Two different varactor diode structures: (a) Single, (b) Anti-series 18
Figure 5. Schematic of designed power amplifier for DLM 20
Figure 6. Optimum load impedances at each output power(▲) and implemented optimum impedance locus(X) 21
Figure 7. Photograph of realized PA 22
Figure 8. Control voltage requirement along to input power 23
Figure 9. Static measurement result of designed PA 25
Figure 10. Non-linearity effect of RF power amplifier 27
Figure 11. General block diagram of digital pre-distortion 28
Figure 12. Block diagram of indirect memory DPD 30
Figure 13. Simulation result of memory DPD, Spectrum 36
Figure 14. Simulation results of memory DPD: AMAM/AMPM 37
Figure 15. Measurement set-up block diagram 40
Figure 16. Time alignment issue 42
Figure 17. Efficiency and linearity variation along to time mismatch 43
Figure 18. Dynamic load modulation measurements of W-CDMA 44
Figure 19. Dynamic load modulation measurements of W-CDMA 45
Figure 20. Experimental results of DLM with DPD: AMAM/AMPM 46
초록보기 더보기
In this paper, design method of high efficiency and high linearity RF power amplifier(PA) is presented. This PA operates at 1.85 GHz using GaN high-electron-mobility transistor(HEMT). High efficiency is achieved at not only maximum output power but also back-off region with dynamic load modulation(DLM) technique. Output tunable matching network is composed of varactor diode, which junction capacitance are controlled by junction capacitance. For the best DLM performance, accurate control signals are chosen through measurement. To improve bad linearity due to efficiency-oriented impedance matching, digital pre-distortion(DPD) technique is performed. Considering memory effect, indirect memory DPD algorithm is selected with non-linearity order 9 and memory depth 3. Whole signal processes are done with MATLAB and algorithm is examined through simulations. The PA is measured with 3.84 MHz W-CDMA signal at 7.4 dB peak-to-average power ratio(PAPR). A time alignment algorithm is adopted to compensate time delay between RF path and control signal path. The measurement shows that 44 % power-added efficiency(PAE) at 30 dBm output power with -45 dBc adjacent channel leakage ratio(ACLR). The PAE has improved 12 % at 7 dB back-off region.
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