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Title Page
Contents
Abstract 9
Chapter 1. INTRODUCTION 11
1.1. Motivation 11
1.2. Background 12
1.2.1. Magnetoresistance 12
1.2.2. Magnetic Tunnel Junction 17
1.2.3. Switching mechanisms 24
1.2.4. Digital logic 32
Chapter 2. UNIVERSAL MTJ LOGIC GATE 35
2.1. Basic logic cell and operation 35
2.1.1. Macro-model 38
2.2. Functional logic designs and operations 40
2.2.1. Design considerations 41
2.2.2. Single-MTJ-based logic gate 43
2.2.3. Dual-MTJ-based logic gate 52
2.3. Summary and discussion 55
Chapter 3. IMPLEMENTATION OF THE FULL ADDER BASED ON THE UNIVERSAL MTJ LOGIC GATES 58
3.1. Full-adder 58
3.2. Universal MTJ logic gate-based full-adder 60
3.2.1. Design and verification: "Type 1" 62
3.2.2. Design and verification: "Type 2" 63
3.2.3. Analysis of power consumption 65
3.3. Summary and discussion 69
Chapter 4. CONCLUSIONS 70
REFERENCES 72
Table 1.1. All of the binary Boolean logic operations based on two inputs 34
Table 2.1. A list of the configurations for the universal logic gates to present 16 binary... 56
Fig. 1.1. Monumental R-H curve for GMR effect, its multilayered structure... 13
Fig. 1.2. The schematic sketches of magnetic tunnel junction and the spin-dependent... 15
Fig. 1.3. The direction of MS is defined with the angle γ relative to a unique axis 19
Fig. 1.4. Schematic energy diagrams and the easy axes depending on the sign of the... 20
Fig. 1.5. In writing process, (a) two Oersted fields are generated from both of lines to... 25
Fig. 1.6. (a) General structure of MTJ for the thermally-assisted switching, and (b) its... 26
Fig. 1.7. (a) Transverse components of spin-polarized electrons exert a spin-transfer... 28
Fig. 1.8. The schematic energy diagram of VCMA switching process 31
Fig. 2.1. (a) A simple sketch for our 3-terminal MTJ. (b) The multilayered structure... 36
Fig. 2.2. (a) An I-V curve of the MTJ logic cell. The magnetization states are... 38
Fig. 2.3. The simulation results of the MTJ macro-model. (b) By applying... 40
Fig. 2.4. 3 supplementary circuits transform the MTJ logic cell into the logic gate 41
Fig. 2.5. The simulated waveforms of (a) "AND" gate and (b) "NAND" gates 44
Fig. 2.6. The simulated waveforms of (a) "OR" gate and (b) "NOR" gates 45
Fig. 2.7. The simulated waveforms of (a) "V IMP H" gate and (b) "V NIMP H" gates 46
Fig. 2.8. The simulated waveforms of (a) "H IMP V" gate and (b) "H NIMP V" gates 48
Fig. 2.9. The simulated waveforms of (a) "V" gate and (b) "NOT V" gates 49
Fig. 2.10. The simulated waveforms of (a) "H" gate and (b) "NOT H" gates 50
Fig. 2.11. The simulated waveforms of (a) "TRUE" gate and (b) "FALSE" gates 52
Fig. 2.12. (a) An illustration of the dual-MTJ-based universal logic gate. RMA and... 53
Fig. 2.13. The simulated waveforms of (a) "XNOR" gate and (b) "XOR" gate 55
Fig. 3.1. The conventional expressions and the truth table for the half-adder 59
Fig. 3.2. (a) The conventional expressions and the truth table for the full-adder. (b) The... 60
Fig. 3.3. Another type of the symbolic representation of the full-adder. 2 MUXs are... 61
Fig. 3.4. Construction with the MTJ logic gates to fulfill the "type 1" representation of... 62
Fig. 3.5. The simulated waveforms of the operation of the "type 1" MTJ logic gate-... 63
Fig. 3.6. Efficient construction with the MTJ logic gates considering the... 64
Fig. 3.7. The sensing amplifier (SA) enables the "XOR" gates to simultaneously... 65
Fig. 3.8. (a) a flipped voltage follower (FVF). The transistor MB acts as a current... 66
Fig. 3.9. (a) The simulated operation waveforms. (b) The results of power analysis for... 67
Fig. 3.10. (a) The simulated operation waveforms. (b) The results of power analysis for... 68
초록보기 더보기
The magnetic tunnel junction (MTJ) has been renowned for being one of the most suitable candidates for beyond complementary metal oxide semiconductor (CMOS). Its properties such as non-volatility, high speed, and zero standby power have gained much attention from industries and academia. As a matter of fact, MTJ has been replaceable for conventional memory technology which consumes a significantly high static power as it continues to scale down. Thus, many studies have progressed to sustain its use to develop MTJ-based memory (e.g. STT-MRAM) practical and marketable. On the other hand, a relatively few researches have achieved practical logic applications which infers that the MTJ's simple resistor like structure makes it difficult to implement unlike the application of memory. In this work, we present MTJ logic cell with 3 terminals operated by the application of external magnetic field and voltage bias. The complementary of both inputs produces 7 binary Boolean logic operations. Additionally, 3 supplementary circuits have been employed to form the structure of universal MTJ logic gate which allows 16 logic operations (a complete set of two input-based Boolean logic operations) to perform in just one logic stage. This completeness could make a logic design simpler because each MTJ logic gate is considered as a building block, so only a gate-level design is allowed without considering the lower abstraction level. Mixed simulations with a compact model have verified all of the operations. In order to accomplish more complex logic operations such as an arithmetic function, a full-adder (FA) circuit has been chosen as an example and constructed by the MTJ logic gates in 2 ways: a conventional design with 5 gates and an advanced design with 2 gates. The reduced gate counts in the latter are achieved by the reconfigurable capability which is a major advantage of the universal MTJ logic gate. The power consumptions have also been analyzed for those designs to compare with conventional CMOS-based FA as a reference.
Considering the universal logic gate in this thesis as a pioneer, we are still finding a way to enhance the performance and to apply an efficient non-volatile logic algorithm. We believe that these efforts can accelerate the utilization of the MTJ logic gates for practical applications and partly replace the conventional logic gates where the efficiency is well appreciated.
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