본문 바로가기 주메뉴 바로가기
22대 대한민국 국회 국회정보길라잡이 국회의원검색
회원가입 로그인
HOME

정보검색

소장정보 검색

국회도서관 홈으로 정보검색 소장정보 검색
결과 내 검색 동의어 포함
결과 내 검색 동의어 포함

-

목차보기

Contents

Optimization of Double Gate Vertical Channel Tunneling Field Effect Transistor (DVTFET) with Dielectric Sidewall / Xiangyu Wang ; Wonhee Cho ; Hyoung Won Baac ; Dongsun Seo ; Il Hwan Cho 1

Abstract 1

I. INTRODUCTION 1

II. SIMULATION STRUCTURE 1

III. SIMULATION AND DISCUSSION 2

V. CONCLUSIONS 5

REFERENCES 5

[저자소개] 6

초록보기

In this paper, we propose a novel double gate vertical channel tunneling field effect transistor (DVTFET) with a dielectric sidewall and optimization characteristics. The dielectric sidewall is applied to the gate region to reduced ambipolar voltage (Vamb) and double gate structure is applied to improve on-current (ION) and subthreshold swing (SS). We discussed the fin width (WS), body doping concentration, sidewall width (Wside), drain and gate underlap distance (Xd), source doping distance (XS) and pocket doping length (XP) of DVTFET. Each of device performance is investigated with various device parameter variations. To maximize device performance, we apply the optimum values obtained in the above discussion of a optimization simulation. The optimum results are steep SS of 32.6 mV/dec, high ION of 1.2 10-3 A/ m and low Vamb of -2.0 V.

권호기사

권호기사 목록 테이블로 기사명, 저자명, 페이지, 원문, 기사목차 순으로 되어있습니다.
기사명 저자명 페이지 원문 목차
Process Variation on Arch-structured Gate Stacked Array 3-D NAND Flash Memory Myung-Hyun Baek, Do-Bin Kim, Seunghyun Kim, Sang-Ho Lee, Byung-Gook Park pp.260-264

보기
Contact Resistance Reduction between Ni–InGaAs and n-InGaAs via Rapid Thermal Annealing in Hydrogen Atmosphere Jeongchan Lee, Meng Li, Jeyoung Kim, Geonho Shin, Ga-won Lee, Jungwoo Oh, Hi-Deok Lee pp.283-287

보기
Implementation of an Integrated Pressure-sensor System Adapted to the Optimum Sensitivity Sung-Hee Hong, Chun-Hyung Cho pp.186-191

보기
Implementation of Neuromorphic System with Si-based Floating-body Synaptic Transistors Jungjin Park, Hyungjin Kim, Min-Woo Kwon, Sungmin Hwang, Myung-Hyun Baek, Jeong-Jun Lee, Taejin Jang, Byung-Gook Park pp.210-215

보기
Design and Analysis of AlGaN/GaN MIS HEMTs with a Dual-metal-gate Structure Young In Jang, Sang Hyuk Lee, Jae Hwa Seo, Young Jun Yoon, Ra Hee Kwon, Min Su Cho, Bo Gyeong Kim, Gwan Min Yoo, Jung-Hee Lee, In Man Kang pp.223-229

보기
A Study on Thermal Stability Improvement in Ni Germanide/p-Ge using Co interlayer for Ge MOSFETs Geon-Ho Shin, Jeyoung Kim, Meng Li, Jeongchan Lee, Ga-Won Lee, Jungwoo Oh, Hi-Deok Lee pp.277-282

보기
Optimization of Double Gate Vertical Channel Tunneling Field Effect Transistor (DVTFET) with Dielectric Sidewall Xiangyu Wang, Wonhee Cho, Hyoung Won Baac, Dongsun Seo, Il Hwan Cho pp.192-198

보기
Transient Simulation of Graphene Sheets using a Deterministic Boltzmann Equation Solver Sung-Min Hong pp.288-293

보기
Si_1-x_Geₓ Positive Feedback Field-effect Transistor with Steep Subthreshold Swing for Low-voltage Operation Sungmin Hwang, Hyungjin Kim, Dae Woong Kwon, Jong-Ho Lee, Byung-Gook Park pp.216-222

보기
Methodology for Extracting Trap Depth using Statistical RTS Noise Data of Capture and Emission Time Constant Dong-Jun Oh, Sung-Kyu Kwon, Hyeong-Sub Song, So-Yeong Kim, Ga-Won Lee, Hi-Deok Lee pp.252-259

보기
AlGaN/GaN-on-Si Power FET with Mo/Au Gate Hyun-Seop Kim, Won-Ho Jang, Sang-Woo Han, Hyungtak Kim, Chun-Hyung Cho, Jungwoo Oh, Ho-Young Cha pp.204-209

보기
InGaAs-based Tunneling Field-effect Transistor with Stacked Dual-metal Gate with PNPN Structure for High Performance Ra Hee Kwon, Sang Hyuk Lee, Young Jun Yoon, Jae Hwa Seo, Young In Jang, Min Su Cho, Bo Gyeong Kim, Jung-Hee Lee, In Man Kang pp.230-238

보기
A Reconfigurable 4^th^ Order ΣΔ Modulator with a KT/C Noise Reduction Circuit Su-Hun Yang, Jae-Hyeon Seong, Kwang-Sub Yoon pp.294-301

보기
Mutually-Actuated-Nano-Electromechanical (MA-NEM) Memory Switches for Scalability Improvement Ho Moon Lee, Woo Young Choi pp.199-203

보기
Characterization of the Vertical Position of the Trapped Charge in Charge-trap Flash Memory Seunghyun Kim, Dae Woong Kwon, Sang-Ho Lee, Sang-Ku Park, Youngmin Kim, Hyungmin Kim, Young Goan Kim, Seongjae Cho, Byung-Gook Park pp.167-173

보기
A Study on Shear-stress Calibration by the Mid-point Measurements in +45/-45 Degree Semiconductor Resistor-pair Chun-Hyung Cho, Ho-Young Cha, Hyuk-Kee Sung pp.180-185

보기
Triple-gate Tunnel FETs Encapsulated with an Epitaxial Layer for High Current Drivability Jang Woo Lee, Woo Young Choi pp.271-276

보기
CMOS Analog Integrate-and-fire Neuron Circuit for Driving Memristor based on RRAM Min-Woo Kwon, Myung-Hyun Baek, Jungjin Park, Hyungjin Kim, Sungmin Hwang, Byung-Gook Park pp.174-179

보기
Experimental Investigation of Physical Mechanism for Asymmetrical Degradation in Amorphous InGaZnO Thin-film Transistors under Simultaneous Gate and Drain Bias Stresses Chan-Yong Jeong, Hee-Joong Kim, Jeong-Hwan Lee, Hyuck-In Kwon pp.239-244

보기
Electrical Characteristics of SiO₂/4H-SiC Metal-oxide-semiconductor Capacitors with Low-temperature Atomic Layer Deposited SiO₂ Yoo Jin Jo, Jeong Hyun Moon, Ogyun Seok, Wook Bahng, Tae Joo Park, Min-Woo Ha pp.265-270

보기
Investigation of Nb-Zr-O Thin Film using Sol-gel Coating Joonam Kim, Kenichi Haga, Eisuke Tokumitsu pp.245-251

보기
Novel Pass-transistor Logic based Ultralow Power Variation Resilient CMOS Full Adder Manisha Guduri, Aminul Islam pp.302-317

보기

참고문헌 (16건) : 자료제공( 네이버학술정보 )

참고문헌 목록에 대한 테이블로 번호, 참고문헌, 국회도서관 소장유무로 구성되어 있습니다.
번호 참고문헌 국회도서관 소장유무
1 Vertical tunnel field-effect transistor 네이버 미소장
2 Experimental Demonstration of p-Channel Germanium Epitaxial Tunnel Layer (ETL) Tunnel FET With High Tunneling Current and High ON/OFF Ratio 네이버 미소장
3 Silicon surface tunnel transistor 네이버 미소장
4 Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec 네이버 미소장
5 Vertical type double gate tunnelling FETs with thin tunnel barrier 네이버 미소장
6 IEEE Transactions on Electron Devices information for authors 네이버 미소장
7 Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric 네이버 미소장
8 Asymmetric dual-gate tunneling FET with improved performance 네이버 미소장
9 Reduction of ambipolar characteristics of vertical channel tunneling field-effect transistor by using dielectric sidewall 네이버 미소장
10 K. Boucart and A. M. Ionescu, “Length scaling of the double gate tunnelFETwith a high-k gate dielectric,” SolidState Electron, vol. 51,no. 11, pp.1500–1507, Nov./Dec. 2007. 미소장
11 Santa Clara, CA 2014 SILVACO Int. ATLAS User’s Man. 미소장
12 J. Wan, C. Le, A. Zaslavsky, and S. Cristoloveanu, “Tunneling FETs on SOI: Suppression of ambipolar leakage, low-frequency noise behavior, and modeling,” Solid-State Electronics, vol. 65, no. 1, pp. 226-233,Nov. 2011. 미소장
13 Tunnel field-effect transistor without gate-drain overlap 네이버 미소장
14 30-nm Tunnel FET With Improved Performance and Reduced Ambipolar Current 네이버 미소장
15 Improved Subthreshold and Output Characteristics of Source-Pocket Si Tunnel FET by the Application of Laser Annealing 네이버 미소장
16 Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor 네이버 미소장

추천서가 (다양한 추천 자료를 만나보세요)

권호기사보기

권호기사 목록 테이블로 기사명, 저자명, 페이지, 원문, 기사목차 순으로 되어있습니다.
기사명 저자명 페이지 원문 기사목차