표제지
감사의 글
목차
Abstact 6
I. 서론 7
II. Au 나노갭의 디자인 10
1. 맨해턴 패턴의 디자인 10
2. 캐패시터 패턴의 디자인 12
3. 마이크로 플루딕 채널의 디자인 15
III. Au 나노갭의 제작공정 17
1. n+ 영역 제작 20
2. 전극 제작 20
3. ALD 공정 21
4. 석판인쇄 공정 23
IV. 결론 36
참고문헌 37
Table 2.1. The calculated capacitance values at three nanogap sizes 12
Table 3.1. The condition of n+ region doping 20
Table 3.2. DC sputtering for bottom gold electrodes 21
Table 3.3. ALD process for nanogap size definition 22
Table 3.4. Thermal evaporation process for top gold electrodes 23
Table 3.5. Positive photoresist lithography process for electrodes patterning 24
Table 3.6. Wet etching and the etch rates for electrode patterning 29
Table 3.7. SU-8 negative photoresist lithography process for microfluidic channel 32
Fig 1. Two types of nanogaps: planar and vertical structures. 9
Fig 2.1. Layout of Manhattan pattern in vertical gold nanogap 11
Fig 2.2. Layout of the capacitor pattern in the vertical gold nanogap 14
Fig 2.3. Layout of microfluidic pattern and inlets in vertical gold nanogap 16
Fig 3.1. Schematics of the fabrication process flow and an optical photograph of the top view. 18
Fig 3.2. Schematics of the fabrication process flow and an optical photograph of the top view. 19
Fig 3.2. SEM photographs of positive photoresist pattern on p-type bare Si wafer. 25
Fig 3.3. Optical microscope images of positive photoresist patterns on working wafer. 27
Fig 3.4. Optical microscope images of positive photoresist patterns on working wafer 27
Fig 3.5. Photographs image of the vertical gold nanogap patterns. 28
Fig 3.6. Optical microscope images of top views of wet etched electrodes. 31
Fig 3.7. Cross-sectional TEM photographs of 7-nm vertical gold nanogap. 33
Fig 3.8. Schematic of microfluidic chanel process 33
Fig 3.9. Top-view of vertical gold nanogap with microfluidic channel 34