표제지
목차
국문초록 9
제1장 서론 10
1.1. 연구 배경 10
1.2. 논문 구성 11
제2장 기존 SRAM 구조와 주소 구성 12
2.1. Column-interleaving 구조 12
2.2. SRAM 주소의 데이터 경로와 순차적 접근방식 17
제3장 제안된 burst SRAM 19
3.1. 제안된 burst SRAM 기본 동작 19
3.2. 전체 구조와 특징 22
3.3. 제안된 Burst SRAM 구성 34
제4장 제안된 Burst SRAM 시뮬레이션 결과 37
4.1. 전력 비교 37
4.2. 면적 비교 39
4.3. 기존 연구와 비교 40
제5장 결론 41
참고문헌 42
ABSTRACT 47
Table 4-1. Comparison Table 40
Figure 2-1. Conventional SRAM structure with column-interleaving structure. 13
Figure 2-2. Advantages of column-interleaving in the conventional SRAM. 15
Figure 2-3. Unnecessary BL swing and half-select issues in the column-interleaving based SRAM structure. 16
Figure 2-4. Simplified data path of memory address in SRAM based on column inter-leaving. 18
Figure 2-5. Available address configuration and sequential memory access. 18
Figure 3-1. Operating principles of the proposed burst SRAM. 21
Figure 3-2. Overall architecture and key features of the proposed burst SRAM. 23
Figure 3-3. Leakage worst cases for sequential read and write in the proposed burst SRAM. 25
Figure 3-4. BL voltage characteristics in worst leakage scenarios; (a) sequential read and (b) write, (c) sequential writes at different number of cells per BL, and (d) sequen-... 27
Figure 3-5. BL clamper for leakage compensation in the proposed burst SRAM. 29
Figure 3-6. Considerations for the assist technique in the proposed burst SRAM. 31
Figure 3-7. Assist configuration for the proposed burst SRAM. 33
Figure 3-8. Operation failure rate with SRAM assist. 35
Figure 3-9. SRAM assist strength with PVT variation; (a) WLOD and (b) TVC and (c) SBL. 35
Figure 3-10. TVC waveform; (a) cell array current and (b) VCS voltage level. 36
Figure 4-1. Power Comparisons between proposed burst SRAM and conventional SRAM. 38
Figure 4-2. Power Comparisons with varying MUX size. 38
Figure 4-3. Proposed Burst SRAM Layout. 39