표제지
목차
국문초록 10
제1장 서론 11
1.1. 연구 배경 11
1.2. 논문 구성 12
제2장 TP-SRAM의 구조와 기존 TP-SRAM 13
2.1. TP-SRAM의 구조 13
2.2. 기존 TP-SRAM 15
제3장 제안된 8T Transposable SRAM 20
3.1. Array 구조 20
3.1.1. Bit-cell design 20
3.1.2. Bridge 21
3.2. 데이터 재배열과 transposable access 24
3.2.1. Column interleaving 구조에서의 데이터 재배열 24
3.2.2. Array 크기 별 데이터 재배열 및 접근의 경우의 수 24
3.2.3. Read와 write 동작 시의 transposable access 29
3.3. Hardware-efficient Barrel Shifter 31
3.3.1. 구조와 기본 동작 31
3.3.2. 이전 barrel shifter의 unit cell MUX 32
3.3.3. 제안하는 dynamic logic based MUX 기반 barrel shifter 37
제4장 제안된 8T TP-SRAM 시뮬레이션 결과 40
4.1. Barrel Shifter 40
4.1.1. Power 40
4.1.2. Delay 40
4.1.3. Area 40
4.2. 16K 8T TP-SRAM 43
4.2.1. Power 43
4.2.2. Delay 43
4.2.3. Area 43
제5장 결론 46
참고문헌 47
ABSTRACT 50
Figure 1. Two directional data access in the conventional column-interleaved SRAM. 14
Figure 2. Summary of the previous transposable SRAM. 17
Figure 3-1. Data rearrangement. 18
Figure 3-2. Array structure for the integrated I/O based TP-memory. 19
Figure 4. Overall array structure of the proposed 8T TP-SRAM including bit-cell schematic, layout, and signal conditions. 22
Figure 5. Layout of the Prop. 8T SRAM. 23
Figure 6. Data rearrange in the column interleaving structure. 26
Figure 7-1. Data rearrange in the column interleaving structure for NR=NC. 26
Figure 7-2. Data rearrange in the column interleaving structure for NR〈NC. 27
Figure 7-3. Data rearrange in the column interleaving structure for NR〉NC. 28
Figure 8. Bi-directional operation of the barrel shifter. 30
Figure 9. Schematic and operation principle of barrel shifter 33
Figure 10-1. Left rotation. 34
Figure 10-2. Right rotation. 34
Figure 11. Exponential growth of the number of MUX used for barrel shifter. 35
Figure 12. MUX candidates. 36
Figure 13. Domino logic based MUX. 36
Figure 14. Conventional and proposed MUX schematic. 39
Figure 15. Proposed barrel shifter and timing diagram. 39
Figure 16. Layout of proposed barrel shifter. 39
Figure 17-1. Power comparisons between proposed barrel shifter and conventional barrel shifter in 0.9V and 0.6V. 41
Figure 17-2. Delay comparisons between proposed barrel shifter and conventional barrel shifter in 0.9V and 0.6V. 41
Figure 17-3. Proposed 32-bit barrel shifter layout. 42
Figure 17-4. Area comparisons between proposed barrel shifter and conventional barrel shifter. 42
Figure 18-1. Power comparisons between proposed 8T TP-SRAM and conventional TP-SRAM in 0.9V and 0.6V. 44
Figure 18-2. Delay comparisons between proposed 8T TP-SRAM and conventional TP-SRAM in 0.9V and 0.6V. 44
Figure 18-3. Proposed 16K 8T SRAM layout. 45
Figure 18-4. Area comparisons between proposed 8T TP-SRAM and conventional TP-SRAM. 45