Title Page
Contents
ABSTRACT 11
CHAPTER 1. INTRODUCTION 14
CHAPTER 2. EXTRACTION OF INTERFACE TRAP DENSITY THROUGH PHOTO-ENHANCED SUBTHRESHOLD CURRENT IN SI MOSFETS 18
2.1. Introduction 18
2.2. Device Schematic and Characterization of Optical Response under Above-bandgap Photon Illumination 20
2.3. Concept for Extraction of Trap Density through Photo-enhanced Subthreshold Current 22
2.4. Extraction Results and Discussion 28
CHAPTER 3. CAPACITANCE-BASED EXTRACTION TECHNIQUE FOR SPATIAL AND ENERGY DISTRIBUTIONS OF INTERFACE TRAPS IN SI MOSFETS 33
3.1. Introduction 33
3.2. Device Information and Electrical Characteristics 34
3.3. Concept for Simultaneous Extraction of Spatial and Energy Distribution 36
3.4. Extraction Results and Discussion 40
CHAPTER 4. CHARACTERIZATION OF LATERAL TRAP DISTRIBUTION IN AOS TFTS THROUGH CAPACITANCE-VOLTAGE TECHNIQUE COMBINED WITH ADVANCED CHANNEL CONDUCTION FACTOR 44
4.1. Introduction 44
4.2. Characterization of C-V Model with Lumped-element Model by Gate Bias Range 45
4.3. Device Information and Electrical Characteristics 51
4.4. Extraction Process for Advanced Channel Conduction Factor in a-IGZO TFTs 52
CHAPTER 5. CONCLUSION 57
REFERENCES 58
ABSTRACT IN KOREAN 60
LIST OF PUBLISHED JOURNAL PAPERS 62
LIST OF PUBLISHED CONFERENCE PAPERS 63
Table 1. Basic characteristics of the Si MOSFETs that are used to verify the proposed extraction technique. 35
Table 2. Fitting Parameters for the Surface Potential. 42
Figure 1.1. Summary of proposed extraction techniques in this thesis. 16
Figure 2.1. Schematic diagram of the Si MOSFET used to verify the proposed method. 20
Figure 2.2. The current-voltage (I-V) characteristics(semi-log and linear scale) of Si MOSFETs with W/L=10/0.27[µm/µm], about (a) transfer characteristics, (b) output characteristics. 21
Figure 2.3. Energy band diagram of the metal-oxide-semiconductor structure under above-bandgap optical illumination. The photo-responsive region (EC - Eₚₕ 〈 E 〈 EF) can be modulated by VGS. (a)...[이미지참조] 22
Figure 2.4. Conceptual diagram for photo-enhanced subthreshold current technique description. 23
Figure 2.5. A simple energy band diagram to explain the area of the photo-responsive region (a) when applied flat band voltage(VFB) to the gate voltage and (b) when applied positive bias to the gate voltage.[이미지참조] 24
Figure 2.6. Conceptual diagram to explain the extraction process of the interface trap density. 25
Figure 2.7. Conceptual diagram to extract µ₀ for Dtrap(ψS) used to extract interface trap density.[이미지참조] 27
Figure 2.8. (a) Transfer curve in the photo state where the above bandgap photons are applied and in the dark state where no photon is applied. (b) Transfer curve considering PVE through effective substrate... 28
Figure 2.9. The curve of trap-induced current with surface potential (ψS vs. ID,ₚₕ₋ₜ) calculated by the photonic subthreshold I-V characteristics.[이미지참조] 30
Figure 2.10. ψS(VGS) curve to extract energy distribution of traps through subthreshold region drain current.[이미지참조] 30
Figure 2.11. Calculated Dtrap(ψS) for use in calculating the interface trap density (Dit).[이미지참조] 31
Figure 2.12. Extracted Dit through Photo-enhanced Subthreshold Current Technique.[이미지참조] 31
Figure 3.1. Schematic of Si MOSFET and measurement set up for capacitance-voltage characteristics. 34
Figure 3.2. (a) Transfer characteristics (semi-log scale and linear scale), (b) Output characteristics in Si MOSFET with W/L = 100/1.8 [µm/µm]. 34
Figure 3.3. Capacitance-voltage characteristics with various frequencies to confirm the trap response in a Si MOSFET with W/L=100/1.8[µm/µm]. 35
Figure 3.4. Equivalent capacitance circuits at (a) ideal case when there are no traps on the substrate; (b) practical case when there are traps on the substrate. 36
Figure 3.5. (a) Schematic showing the cause of trap due to broken periodicity at Si/SiO₂ interface. (b) Schematic showing the spatial distribution of interface traps in Si MOSFETs. (c) Schematic showing... 36
Figure 3.6. (a) C-V curve that W = 100 [µm], L = 1.8 [µm] Si MOSFETs gate, source, drain, and body is all contacted. (b) ψS-VGS curve calculated by Eq. (3.2).[이미지참조] 40
Figure 3.7. (a) (CS)⁻²-ψS curve to obtain Cg,i(ψS). (b) Ctrap-ψS curve containing the energy distribution of trap density.[이미지참조] 41
Figure 3.8. (a) The curve of Tetd, a parameter for trap position, and ψS. (b) Ctrap-Tetd curve showing the spatial distribution of Ctrap.[이미지참조] 41
Figure 3.9. Fitting process of ψS(Ctrap) to define spatial and energy distributions of traps as a single relationship.[이미지참조] 42
Figure 3.10. 3D plot of (x, ψ, gₜ) showing the spatial and energy distributions of traps extracted using the proposed technique. 43
Figure 4.1. Flow of proposed technique for extraction lateral trap distribution of a-IGZO TFTs. 45
Figure 4.2. Schematic diagram of a-IGZO TFT with distributed element circuit and schematic C-V curve dividing the region of gate bias. 46
Figure 4.3. Equivalent circuit model of a-IGZO TFT according to bias region. (a) Off-state region (VG 〈 Voff), (b) transition region (Voff 〈 VG 〈 Von), (c) on-state region (VG 〉 Von).[이미지참조] 46
Figure 4.4. Circuit of canonical T-line structure to calculate the input impedance of commonly used lumped-element model. 47
Figure 4.5. Simplified a-IGZO TFT model by applying the lumped-element model. 48
Figure 4.6. Equivalent circuit model of measuring equipment and equivalent circuit model of the device to de-embedding the effect of parasitic resistance. 48
Figure 4.7. Equivalent circuit model applying the input admittance model of the lumped-element model to the intrinsic equivalent admittance. 49
Figure 4.8. Equivalent circuit model of a-IGZO TFT showing the region defining the capacitance of the channel(Cch) to define the advanced CCF.[이미지참조] 50
Figure 4.9. Schematic image of a-IGZO TFT with W/L = 30/10[µm/µm] that was used for verification of the proposed method. 51
Figure 4.10. (a) Transfer characteristics, (b) output characteristics in a-IGZO TFT with W/L=30/10[µm/µm]. 51
Figure 4.11. (a) C-V curves in contact with gate, source, and drain, (b) C-V curves in contact with gate and source, and (c) C-V curves in contact with gate and drain in a-IGZO TFT with W/L = 30/10[μm/μm]. 51
Figure 4.12. Curve of capacitance (CLCR) and conductance (GLCR) measured through LCR meter.[이미지참조] 52
Figure 4.13. Curve of H-Function applied to extract parasitic resistance. 53
Figure 4.14. Curve of intrinsic capacitance(Cint) and intrinsic conductance(Gint) with the effect of parasitic resistance(RS,D) removed.[이미지참조] 53
Figure 4.15. Curves of Cch and Rch of a channel where RS,D, Rch, and Cov are de-embedded.[이미지참조] 54
Figure 4.16. Advanced CCF defined after de-embedding all effects of RS,D, Rch, and Cov.[이미지참조] 54
Figure 4.17. Lateral distribution of traps extracted through advanced CCF and Cch(Leff).[이미지참조] 55
Figure 4.18. Equivalent circuit of new impedance model reflecting trap response. 55
Figure 4.19. Equivalent circuit model for each contact configuration. 56