Title Page
Contents
ABSTRACT 13
Chapter 1. Introduction 15
1.1. Motivation 15
1.2. Thesis organization 20
Chapter 2. Fundamentals of Pipelined SAR ADC 22
2.1. Conventional Nyquist ADC Topologies 23
2.1.1. Pipeline ADC 23
2.1.2. Successive approximation register ADC 27
2.1.3. Pipelined SAR ADC 31
2.2. Residue Amplifier in Pipelined SAR ADC 38
2.2.1. Residue transfer function 38
2.2.2. A 12-bit pipelined SAR with conventional residue OTA 43
2.2.3. Residue amplifier topologies 48
2.2.4. Optimization of pipelined SAR ADC using dynamic amplifier 52
Chapter 3. A 7-bit 800MS/s 3-stage pipelined SAR ADC with Temperature Compensated Seven-transistor Dynamic Residue Amplifier 60
3.1. Introduction 60
3.2. Temperature-compensated seven-transistor dynamic residue amplifier 63
3.3. Circuit implementation of overall ADC 73
3.4. Measurement result 76
Chapter 4. A 9-bit 500MS/s 4-stage pipelined SAR ADC with replica biased dynamic amplifiers 85
4.1. Introduction 85
4.2. Fundamental concept of replica-biased dynamic residue amplifier 90
4.2.1. Challenges of cascading multiple dynamic amplifier 90
4.2.2. Concept of replica-biased dynamic amplifier 95
4.3. Replica-biased dynamic amplifier realizations 99
4.3.1. Output common-mode replica-biasing 99
4.3.2. Differential-gain replica-biasing 104
4.3.3. Correlation between common-mode replica and gain replica 109
4.4. ADC architecture and implementation 111
4.5. Measurement result 115
Chapter 5. Conclusion 132
References 134
Abstract (in Korean) 143
Table 〈2-1〉 Parameter values for three types of pipelined SAR ADCs 55
Table 〈2-2〉 Power consumption of 3-3-3 structure 55
Table 〈3-1〉 Comparison table with other ADCs 82
Table 〈4-1〉 Performance summary and comparison table 126
〈Figure. 1-1〉 Per-lane transfer rate of high-speed serial links over the years 17
〈Figure. 1-2〉 An example of ADC/DSP based serial link receiver 18
〈Figure. 1-3〉 Trends in ADC resolution versus sampling rate 19
〈Figure. 2-1〉 Conventional N·M-bit pipeline ADC architecture 25
〈Figure. 2-2〉 (a) 1-bit sub-ADC without redundancy and (b) 1.5-bit per stage with 1-bit redundancy 26
〈Figure. 2-3〉 (a) A block diagram of a typical N-bit SAR ADC and (b) a signal diagram 29
〈Figure. 2-4〉 Architecture of N-bit loop-unrolled SAR ADC 30
〈Figure. 2-5〉 Input capacitance for SAR ADC based on resolution and required for thermal noise limit 35
〈Figure. 2-6〉 a survey of the total input capacitance of previously published medium-resolution ADC papers in ISSCC and VLSI from 2000 to 2023 36
〈Figure. 2-7〉 (a) A typical N+M-R-bit, 2-stage pipelined SAR ADC architecture and (b) clock diagram 37
〈Figure. 2-8〉 An example of the residue transfer function for a 3-bit pipelined SAR ADC 41
〈Figure. 2-9〉 Residue plot provides useful information for detecting several types of errors in pipelined SAR ADC, including (a) ideal residue plot, (b) offset... 42
〈Figure. 2-10〉 (a) The architecture of the 12-bit pipelined SAR ADC architecture, (b) The clock diagram of the pipelined SAR ADC, (c) The... 46
〈Figure. 2-11〉 (a) The simulated residue transfer function of 2-stage pipelined SAR ADC and (b) The simulated ADC spectrum with 473kHz input... 47
〈Figure. 2-12〉 Classification and pros and cons of residue amplifiers in various types 50
〈Figure. 2-13〉 Four types of residue amplifier (a) closed loop OTA, (b) ring amplifier, (c) static open loop amplifier and (d) dynamic amplifier 51
〈Figure. 2-14〉 Block diagram of three design examples using a dynamic residue amplifier for power optimization (a) 2-2-2-2-3, (b) 3-3-3, (c) 4-4 56
〈Figure. 2-15〉 Estimated power consumption for three types of structures (a) 2-2-2-2-3, (b) 3-3-3, (c) 4-4 57
〈Figure. 3-1〉 (a) Conventional 5T-DA, (b) 7T-DA with kickback noise canceling capacitors 67
〈Figure. 3-2〉 (a) Frequency tripler utilizing CC for gain boosting of the buffer amplifier, (b) Comparator with kickback cancellated pre-amplifier[이미지참조] 68
〈Figure. 3-3〉 Simulated input waveforms for 5T-DA and 7T-DA 69
〈Figure. 3-4〉 (a) Simulated differential input and output of 5T-DA and 7T-DA and (b) Comparison of output linearity error 70
〈Figure. 3-5〉 Circuit implementation of 7T-DA with on-chip LDO and pulse generator 71
〈Figure. 3-6〉 (a) Simulated CKP pulsewidth and (b) DA gain over temperature with on-chip LDO and pulse generator[이미지참조] 72
〈Figure. 3-7〉 Architecture and timing diagram of the 3-stage 7-bit pipelined SAR ADC 75
〈Figure. 3-8〉 Photomicrography and layout of the prototype 3-stage 7-bit pipelined SAR ADC 78
〈Figure. 3-9〉 Power breakdown of the chip 79
〈Figure. 3-10〉 Measured output spectrum with (a) 388MHz and (b) 2.25GHz inputs 80
〈Figure. 3-11〉 (a) Measured SNDR/SFDR vs. input frequency, (b) Measured SNDR/SFDR vs. sampling frequency and (c) Measured SNDR over temperature 81
〈Figure. 4-1〉 A survey on the number of stages in the recently published pipelined SAR ADCs 89
〈Figure. 4-2〉 (a) A conventional dynamic amplifier and (b) Illustrated comparison of the output and input signals for high and low VINCM, (c)...[이미지참조] 93
〈Figure. 4-3〉 (a) A chain of three cascaded DAs and (b) Simulated VOUTCM of each stage versus VINCM of the first stage[이미지참조] 94
〈Figure. 4-4〉 (a) A conceptual diagram of the replica-biased DA scheme and (b) Clock and signal diagram of the replica DA circuit 98
〈Figure. 4-5〉 (a) VOUTCM replica-biasing circuit and (b) Implementation details of the VOUTCM replica-biasing circuit[이미지참조] 102
〈Figure. 4-6〉 Simulated waveforms of VOUTCM replica circuit[이미지참조] 103
〈Figure. 4-7〉 (a) Differential gain replica-biasing circuit and (b) Implementation details of the differential gain replica-biasing circuit 107
〈Figure. 4-8〉 Simulated waveforms of the differential gain replica circuit 108
〈Figure. 4-9〉 Architecture and timing diagram of the 4-stage pipelined SAR ADC with replica circuits 114
〈Figure. 4-10〉 Comparator offset simulation using monte-carlo technique 114
〈Figure. 4-11〉 Chip micrograph and layout of the prototype ADC 119
〈Figure. 4-12〉 Power breakdown of the chip 120
〈Figure. 4-13〉 ADC output spectra at 500MS/s with (a) 1.7MHz input and (b) Nyquist input (ADC output is decimated by 32) 121
〈Figure. 4-14〉 Measured DNL and INL of the ADC 122
〈Figure. 4-15〉 Measured SNDR over input common-mode voltage 123
〈Figure. 4-16〉 Measured SNDR versus temperature 124
〈Figure. 4-17〉 Measured SNDR and SFDR versus input signal frequency 125