표제지
국문초록
목차
제1장 서론 11
제1절 PAM-4 signaling 11
제2절 PAM-4 transceiver architecture 14
제2장 Transmitter 16
제1절 PAM-4 transmitter 16
1. BIST 16
2. Mux 17
3. TX driver 18
제2절 Feed Forward Equalizer(FFE) 20
제3장 Clock Generator 22
제1절 Phase Locked Loop 22
제2절 Phase Frequency Detector 24
제3절 Charge Pump 26
제4절 Ring-VCO(Voltage Controlled Oscillator) 30
제5절 LC-PLL 38
제6절 LC-VCO 40
제7절 Cap Bank 42
제8절 Inductor 45
제9절 Phase Noise of LC-VCO 47
제10절 LC-VCO Tuning Curves 48
제4장 Clock and Data Recovery 50
제1절 PLL-based CDR Architecture 50
제2절 Data Transition in PAM-4 52
제5장 PAM-4 Slicer 53
제1절 Receiver 53
제2절 StrongARM Slicer 54
제6장 Layout & Measurements 56
제1절 Layout 56
제2절 Measurements 59
제7장 결론 61
참고문헌 62
ABSTRACT 63
Table 1. Comparison between NRZ and PAM-N signaling 12
Table 2. Performance Comparison of the Ring-VCO 36
Table 3. Performance of the LC-VCO 49
Figure 1. NRZ and PAM-4 signal 11
Figure 2. Block diagram of transceiver 14
Figure 3. Block diagram of transmitter 16
Figure 4. TX driver architecture 18
Figure 5. TX driver simulation 19
Figure 6. Feed Forward Equalizer architecture 20
Figure 7. Feed Forward Equalizer AC simulation 21
Figure 8. PLL architecture 22
Figure 9. Block diagram of Phase Frequency Detector 24
Figure 10. Block diagram of Charge Pump 26
Figure 11. 2nd Loop Filter[이미지참조] 27
Figure 12. PLL response 28
Figure 13. Block diagram of Ring-VCO 30
Figure 14. Conventional and proposed delay cell 31
Figure 15. Duty cycle of conventional and proposed Ring-VCO 32
Figure 16. Phase noise of conventional Ring-VCO 33
Figure 17. Phase noise of proposed Ring-VCO 34
Figure 18. Proposed Ring-VCO tuning curve 35
Figure 19. LC-PLL architecture 38
Figure 20. LC-VCO circuit 40
Figure 21. Bypass capacitor 41
Figure 22. LC-VCO tuning curves 42
Figure 23. AC simulation of cap bank 43
Figure 24. Symmetric inductor 45
Figure 25. Inductor Q-factor vs frequency 46
Figure 26. Phase noise of LC-VCO 47
Figure 27. Simulated LC-VCO tuning curves 48
Figure 28. PLL-based CDR architecture 50
Figure 29. Data transition in PAM-4 52
Figure 30. 14-nm 25-Gbps PAM-4 transceiver 53
Figure 31. StrongARM Slicer architecture 54
Figure 32. TX layout 56
Figure 33. Ring-VCO layout 57
Figure 34. LC-VCO layout 57
Figure 35. Ring-PLL measurement 59
Figure 36. LC-PLL measurement 60