Title Page
Abstract
Contents
Chapter 1. Introduction 17
1.1. Neuromorphic computing 17
1.2. Synaptic devices 20
1.2.1. Requirement of synaptic devices 20
1.2.2. Synaptic devices 22
1.3. Purpose of research 26
1.4. Dissertation outline 28
Chapter 2. Charge trap flash -based synaptic device and array 30
2.1. Device structure 30
2.2. Fabrication process of charge trap flash memory 33
2.3. Cell characteristics 42
2.4. AND-type flash array 44
Chapter 3. Hardware-based on neural networks 48
3.1. Convolutional neural networks design 48
3.1.1. VGG-9 48
3.1.2. Mapping method for convolutional neural networks 52
3.1.3. Accuracy for charge trap flash-based synaptic device 54
3.2. Impact of Data Retention on Inference 56
3.2.1. Retention characteristics of CTF-based synaptic device 56
3.2.2. Multiple cell mapping method 59
Chapter 4. 3-D stacked Charge Trap Flash Memory 62
4.1. Device structure 62
4.2. Device characteristics 67
4.3. Fabrication process of 3-D stacked CTF-based synaptic device 70
4.4. Array characteristics 86
Chapter 5. Conclusion 91
References 93
List of Publications 106
Abstract in Korean 112
Table. 2.1. Operating condition of AND-type flash array. 45
Table. 4.1. Comparison of basic properties of various synaptic devices 66
Table. 4.2. Simulation parameter of 3-D stacked CTF-based synaptic device. 69
Figure. 1.1. Schematics of (a) von Neumann architecture and (b) neural networks. 19
Figure. 1.2. Requirement of synaptic devices for neuromorphic system. 21
Figure. 1.3. Memristor devices (a) resistive random-access memory [25] and (b) phase change memory. 23
Figure. 1.4. Schematics of (a) NOR-type flash array, (b) NAND-type flash array and (c) AND-type flash array. 25
Figure. 2.1. (a) 3-D schematic of proposed of CTF-based synaptic device and (b) Fabrication flow of CTF-based synaptic device. 32
Figure. 2.2. Schematics of (a) global marker patterning and (b) buried oxide and poly-Si active layer deposition process. 34
Figure. 2.3. Schematics of (a) active layer patterning and (b) gate dielectric layers deposition process. 36
Figure. 2.4. Schematics of (a) gate material deposition process and patterning and (b) ion implantation process. 38
Figure. 2.5. schematics of ILD deposition process and patterning 39
Figure. 2.6. TEM cross-section image of the fabricated CTF-based synapse device. 41
Figure. 2.7. (a) ISPP characteristics of the fabricated device and (b) Conductance modulation with ISPP. 43
Figure. 2.8. Schematic of AND-type flash array. 45
Figure. 3.1. Schematic diagram of convolutional neural network using VGG-9 architecture. 49
Figure. 3.2. Schematic of the mapping method for implementing (a) the hardware-based CNN and (b) the hardware-based average pooling. 53
Figure. 3.3. Recognition accuracy with different (a) weight quantization precision and (b) output quantization precision. 55
Figure. 3.4. (a) Data retention characteristics (VTH), (b) Retention decay parameter (D) for different synaptic weight values, and (c) Data retention characteristics.[이미지참조] 58
Figure. 3.5. (a) Multiple cell mapping method, (b) Data retention characteristics for single mapping method, (c) Data retention characteristics for multiple... 61
Figure. 4.1. (a) Bird's eye view of 3-D stacked CTF-based synaptic device and (b) Schematic of 3-D stacked CTF-based synaptic device. 64
Figure. 4.2. Top view image of 3-D stacked CTF-based synaptic device. 65
Figure. 4.3. (a) I-V characteristic of 3-D stacked CTF-based synaptic devices and (b) Operation method of 3-D stacked CTF-based synaptic devices. 67
Figure. 4.4. Schematics of (a) global marker patterning and (b) multi-layer O/N stack deposition process. 72
Figure. 4.5. Schematic of (a) active region patterning and (b) active material deposition and CMP process. 74
Figure. 4.6. Schematic of (a) dividing for the synaptic device₁ and synaptic device₂ and (b) dividing for the Tr₁, Tr₂, Tr₃ and Tr₄. 77
Figure. 4.7. Schematic of (a) gap fill for trench and CMP process and (b) dividing for left and right region. 79
Figure. 4.8. Schematic of 1st~3rd layer formation.[이미지참조] 80
Figure. 4.9. Schematic of (a) oxide wet etch and (b) amorphous-Si wet etch. 82
Figure. 4.10. Schematic of (a) oxide etch back process and nitride wet etch process and (b) gate dielectric and metal deposition process. 84
Figure. 4.11. Schematic of (a) program operation scheme of 3-D stacked CTF-based synaptic device and (b) erase operation scheme of 3-D stacked CTF-... 88
Figure. 4.12. (a) Schematic of the schematic of a 3-D stacked CTF-based synaptic device, (b) Change of threshold voltages of cells in 3-D stacked CTF-based... 89
Figure. 4.13. (a) Schematic of the schematic of a 3-D stacked CTF-based synaptic device, (b) Change of threshold voltages of cells in 3-D stacked CTF-based... 90