Title Page
Contents
ABSTRACT 10
Chapter 1. Introduction 12
1.1. Motivation 12
1.2. Thesis Organization 13
Chapter 2. Timing-Skew Calibration for Time-Interleaved ADC 15
2.1. Time-Interleaved ADC 15
2.1.1. Introduction 15
2.1.2. Pros and Cons of TIADC 18
2.2. Timing-Skew Calibration 20
2.2.1. Foreground vs. Background 20
2.2.2. Conventional Background Timing-Skew Calibration 22
Chapter 3. Fractional Delay FIR Filter Based Background Timing-Skew Calibration 26
3.1. FIR Filter 26
3.1.1. Filter 26
3.1.2. Fractional Delay FIR Filter 28
3.2. Proposed Timing-Skew Calibration 31
3.3. Simulation Results 34
Chapter 4. Digital-to-Time Converter for Timing-Skew Correction 38
4.1. Digital-to-Time Converter 38
4.1.1. Introduction 38
4.1.2. Regulated-Constant-Slope DTC 40
4.1.3. DTC Replica Feedback Loop 42
4.2. Delay Measurement Circuit 45
4.3. Measurement Results 47
Chapter 5. Conclusion 53
References 54
Abstract (in Korean) 56
〈Table 2-1〉 Tone frequency according to the error source 20
〈Table 3-1〉 Timing-skew sign according to the sign of D and e 33
〈Table 3-2〉 Performance summary and comparison table 36
〈Table 4-1〉 Performance summary and comparison table 51
〈Figure 2-1〉 Architecture of ADC 15
〈Figure 2-2〉 Architecture of TIADC and timing diagram 17
〈Figure 2-3〉 Timing mismatch in TIADC 19
〈Figure 2-4〉 Spectrum simulation result with timing mismatch (1σ=3ps) 19
〈Figure 2-5〉 Foreground calibration 21
〈Figure 2-6〉 Background calibration 21
〈Figure 2-7〉 Calibration technique using auto-correlation 22
〈Figure 2-8〉 Calibration technique using SS-LMS 23
〈Figure 3-1〉 Analog filter 26
〈Figure 3-2〉 Digital filter 27
〈Figure 3-3〉 Impulse response 28
〈Figure 3-4〉 Shaped pulse at input and output modeled by Matlab (tap=19 and u=0) 29
〈Figure 3-5〉 Response of fractional delay FIR filter according to fractional delay modeled by Matlab (tap=19) 29
〈Figure 3-6〉 Overall Architecture of the proposed timing-skew calibration 31
〈Figure 3-7〉 Calibration concept 32
〈Figure 3-8〉 FFT result of behavioral modeling according to timing-skew calibration 35
〈Figure 3-9〉 Layout view of the timing-skew calibration 35
〈Figure 4-1〉 Architecture of the receiver with MET-CDR 39
〈Figure 4-2〉 Architecture of DTC-based all-digital PLL 40
〈Figure 4-3〉 Block diagram of core 40
〈Figure 4-4〉 The transistor-level circuit of a 6-bit DTC 41
〈Figure 4-5〉 Pre-charging and discharging of the programmable CDAC 42
〈Figure 4-6〉 The details of the replica feedback loop 43
〈Figure 4-7〉 The timing diagram of replica feedback loop 44
〈Figure 4-8〉 Simulation results of Vctrl and full scale according to temperature 44
〈Figure 4-9〉 Architecture of delay measurement circuit 45
〈Figure 4-10〉 Timing diagram of delay measurement circuit 46
〈Figure 4-11〉 Simulation result of behavioral modeling 46
〈Figure 4-12〉 Die micrograph 48
〈Figure 4-13〉 Power breakdown of the chip 49
〈Figure 4-14〉 Measurement result of DTC linearity 49
〈Figure 4-15〉 Measured full-scale variation versus supply voltage change 50
〈Figure 4-16〉 Measured full-scale variation versus temperature change 50