Title Page
Contents
ABSTRACT 10
Chapter 1. Introduction 11
1.1. Motivation 11
1.2. Thesis Organization 12
Chapter 2. Fundamentals of Pipelined SAR ADC and TIADC 14
2.1. Pipelined SAR ADC 14
2.1.1. Introduction 14
2.1.2. Residue Amplifier in Pipelined SAR ADC 17
2.2. TIADC 19
Chapter 3. A 7.9-ENOB 1.5GS/s Common-Mode and Temperature Insensitive Pipelined SAR ADC 22
3.1. Overall Architecture 22
3.2. Residue Amplifier and V INCM -Aware Reset Voltage Generator 26
3.3. Temperature-Sensor-Based Stage Gain Compensation 33
3.4. Measurement Results 36
Chapter 4. A 6.4-ENOB 14GS/s TI Pipelined SAR ADC with a Gain-Enhanced Source Follower and a Flip-Flop-Based Multi-Phase Clock Generator 45
4.1. Overall Architecture and Multi-Phase Clock Generator 45
4.2. Gain-Enhanced Source Follower 48
4.3. Slice ADC and Temperature Compensation 51
4.4. Measurement Results 52
Chapter 5. Conclusion 61
References 62
Abstract (in Korean) 66
〈Table 3-1〉 Performance summary and comparison with prior works 42
〈Table 4-1〉 Performance summary and comparison with prior works 59
〈Figure. 2-1〉 (a) A block diagram of a traditional top-plate sampling N-bit SAR ADC and (b) its timing diagram 15
〈Figure. 2-2〉 (a) A block diagram of a typical N+M-bit, 2-stage pipelined SAR ADC and (b) timing diagram 17
〈Figure. 2-3〉 (a) A conventional DA and (b) its timing diagram 18
〈Figure. 2-4〉 (a) A 64-channel 10GS/s TIADC and (b) its timing diagram 19
〈Figure. 3-1〉 Overall architecture of the proposed five-stage pipelined SAR ADC 23
〈Figure. 3-2〉 (a) Implementation of four 2-bit sub-SAR ADCs and (b) its timing diagram 25
〈Figure. 3-3〉 Schematic of the complementary DA 27
〈Figure. 3-4〉 (a) Schematic and (b) simplified operation of the proposed VINCM-aware reset voltage generation[이미지참조] 29
〈Figure. 3-5〉 Gain error and available VINCM range of the DA over VINCM[이미지참조] 30
〈Figure. 3-6〉 VOUTCM of each stage DA and 3dB SNDR drop boundary over VINCM of the ADC without VINCM compensation[이미지참조] 31
〈Figure. 3-7〉 VOUTCM of each stage DA and 3dB SNDR drop boundary over VINCM of the ADC with VINCM -aware reset generation at the first stage DA[이미지참조] 32
〈Figure. 3-8〉 (a) Gain error and (b) |THD| of DA over VINCM with and without VINCM -aware reset generation[이미지참조] 32
〈Figure. 3-9〉 (a) Block diagram of 5-bit resistor-based temperature sensor and (b) VPTAT over temperature[이미지참조] 34
〈Figure. 3-10〉 (a) Schematic of programmable delay and (b) DA gain over DTC input for three different temperatures 35
〈Figure. 3-11〉 Photomicrography and layout of the prototype five-stage pipelined SAR ADC 37
〈Figure. 3-12〉 Power breakdown of the prototype ADC 38
〈Figure. 3-13〉 Measured output spectrum with Nyquist input 38
〈Figure. 3-14〉 Measured DNL and INL of the ADC normalized to 9-bit resolution 39
〈Figure. 3-15〉 Measured SNDR and SFDR over input frequency 39
〈Figure. 3-16〉 Measured SNDR with VINCM compensation and simulated SNDR without VINCM compensation over VINCM[이미지참조] 40
〈Figure. 3-17〉 (a) Measured temperature sensor output and (b) T2D encoding map found by foreground calibration 40
〈Figure. 3-18〉 Measured temperature sweep of ADC with and without T2D encoding for three random chips 41
〈Figure. 3-19〉 Comparison of FoMW and FoMS with state-of-the-art ADCs[이미지참조] 41
〈Figure. 4-1〉 Overall architecture of the proposed TI pipelined SAR ADC 46
〈Figure. 4-2〉 (a) Timing diagram of the front-end sampler and slice ADC and (b) flip-flop-based MPCG 47
〈Figure. 4-3〉 Circuit schematic of the proposed GESF 49
〈Figure. 4-4〉 Input network from VIN to gate of CS amplifier forming band- pass characteristic[이미지참조] 49
〈Figure. 4-5〉 (a) Simulated gain comparison and (b) simulated harmonic distortion comparison 50
〈Figure. 4-6〉 (a) Monte Carlo simulation of DA's gain over temperature with one-point calibration and (b) with three-point calibration 52
〈Figure. 4-7〉 Die photograph 53
〈Figure. 4-8〉 Measurement setup 54
〈Figure. 4-9〉 (a) Measured FFT for Nyquist input at FS=12GHz and (b) at FS=14GHz[이미지참조] 55
〈Figure. 4-10〉 Measured input frequency sweep at FS=14GHz[이미지참조] 56
〈Figure. 4-11〉 Measured DNL and INL at FS=14GHz[이미지참조] 56
〈Figure. 4-12〉 Power breakdown 57
〈Figure. 4-13〉 (a) Measured temperature sensor digital output versus temperature and (b) the noise performance 57
〈Figure. 4-14〉 Measured SNDR degradation over temperature at FS=12GHz with three different calibrations[이미지참조] 58
〈Figure. 4-15〉 Comparison of FoMW and FoMS with state-of-the-art ADCs[이미지참조] 58