표제지
목차
국문초록 10
제1장 서론 11
1.1. 연구 배경 11
1.2. 논문 구성 12
제2장 딥러닝 가속기를 구성하는 MAC Unit 13
2.1. 딥러닝 네트워크의 구조 13
2.2. MAC unit의 구조 및 기존 연산 과정 16
제3장 제안된 Stochastic Computing 기반 MAC unit 20
3.1. Stochastic Computing 20
3.1.1. Stochastic Number 20
3.1.2. Stochastic Number Generator 21
3.2. Stochastic Computing 기반 곱셈기 23
3.2.1. 기본 stochastic multiplier의 구조와 원리 23
3.2.2. Sign-magnitude format의 stochastic multiplier 23
3.3. 제안된 Stochastic computing 기반 덧셈기 26
3.3.1. 기존 Stochastic Adder 구조 26
3.3.2. Bitonic Sorter를 적용한 Stochastic Adder 33
3.3.3. 제안하는 Gating 기반 Stochastic Adder와 Bit Reduction 적용 36
제4장 제안된 Stochastic MAC 시뮬레이션 결과 38
4.1. Stochastic Adder 38
4.1.1. Area 38
4.1.2. Power 38
4.2. Stochastic MAC 40
4.2.1. Area 40
4.2.2. Power 40
4.3. Accuracy Comparison 43
제5장 결론 44
참고문헌 45
ABSTRACT 48
Table 1. Accuracy Comparison between binary MAC and stochastic MAC. 43
Figure 1. Architecture of MLP network. 14
Figure 2. MLP computation with multiplication and addition. 14
Figure 3. Architecture of CNN network. 15
Figure 4. Convolution computation process. 15
Figure 5-1. MAC unit applied to CNN. 18
Figure 5-2. MAC unit architecture. 18
Figure 6-1. Binary multiplication architecture with process. 19
Figure 6-2. Binary adder architecture. 19
Figure 7. 7-bit LFSR circuit. 22
Figure 8. Stochastic number generator in sign-magnitude format. 22
Figure 9-1. Basic stochastic multiplier. 25
Figure 9-2. Accuracy drop with basic stochastic multiplier. 25
Figure 10. Sign-magnitude stochastic multiplier with LFSR wiring structure. 25
Figure 11. Stochastic adder using MUX tree. 29
Figure 12. Stochasitc adder using OR gate. 29
Figure 13. Entire BSC adder process. 30
Figure 14-1. Intra-block computation process. 31
Figure 14-2. Intra-block computation circuit. 31
Figure 15-1. Error correction process. 32
Figure 15-2. Error correction process with accuracy drop. 32
Figure 16-1. Ascending and descending circuit. 34
Figure 16-2. Conventional and proposed sorter schematic. 34
Figure 17. Error correction process with top2 sorter applied. 35
Figure 18. Error correction process with gating applied. 35
Figure 19-1. Bit reduction of stochastic number. 37
Figure 19-2. Bit reduction circuit. 37
Figure 19-3. Bit reduction simulation. 37
Figure 20-1. Area comparison between binary adder and stochastic adder. 39
Figure 20-2. Power comparison between binary adder and stochastic adder. 39
Figure 21-1. Area comparison of modules that make up stochastic MAC. 41
Figure 21-2. Power comparison of modules that make up stochastic MAC. 41
Figure 22-1. Area comparison between binary MAC and stochastic MAC. 42
Figure 22-2. Power comparison between binary MAC and stochastic MAC. 42