In this study, we propose a novel 8T ternary SRAM that can process three logic values (0, 1, and 2) with only two additional transistors, compared with the conventional 6T binary SRAM. The circuit structure consists of positive and negative ternary inverters (PTIand NTI, respectively) with carbon-nanotube field-effect transistors, replacing conventional cross-coupled inverters. In logic ‘0’ or ‘2,’the proposed SRAM cell operates the same way as conventional binary SRAM. For logic ‘1,’ it works differently as storage nodes oneach side retain voltages of VDD/2 and VDD, respectively, using the subthreshold current of two additional transistors. By applying theternary system, the data capacity increases exponentially as the number of cells increases compared with the 6T binary SRAM, and theproposed design has an 18.87% data density improvement. In addition, the Synopsys HSPICE simulation validates the reduction in staticpower consumption by 71.4% in the array system. In addition, the static noise margins are above 222 mV, ensuring the stability of thecell operation when VDD is set to 0.9 V