Figure 1-1. Block diagram of mobile system evolution (Courtesy of Postech.) 19

Figure 2-1. Configuration of Class-F and Class-F-1 amplifiers, and a simplified analytical model of an... 24

Figure 2-2. Normalized DC and harmonic current components as a function of the conduction angle. 28

Figure 2-3. Current waveforms for Class-F and Class-F-1 amplifiers as a function of θ＝ωt.(이미지참조) 29

Figure 2-4. Normalized knee voltage for Class-F and Class-F-1 amplifiers.(이미지참조) 30

Figure 2-5. Voltage waveforms for Class-F and Class-F-1 amplifiers as a function of θ＝ωt under different...(이미지참조) 32

Figure 2-6. Drain efficiency and optimum fundament load resistance of Class-F and Class-F-1 amplifiers as...(이미지참조) 33

Figure 2-7. Simplified circuit model of an RF power amplifier with an output impedance matching... 34

Figure 2-8. Normalized nonlinear capacitance versus drain voltage for a GaN device. 35

Figure 2-9. fundament load impedance trajectory with different initial capacitance values. 37

Figure 2-10. Computed voltage waveform with (dashed line) and without (solid line) the effect of... 38

Figure 2-11. Predicted drain efficiency as a function of on-resistance and operating frequency. 40

Figure 2-12. Output power performance of Class-F and Class-F-1 amplifiers 40

Figure 2-13. Simulated time-domain voltage and current waveforms for a (a) Class-F amplifier at α＝π, (b)... 41

Figure 2-14. Calculated and simulated drain efficiencies as a function of the conduction angle 42

Figure 2-15. Proposed Output matching networks for (a) Class-F and (b) Class-F-1 amplifiers.(이미지참조) 43

Figure 2-16. Realized (a) Class-F and (b) Class-F-1 amplifiers(이미지참조) 43

Figure 2-17. Measured and output power, power gain, and drain efficiency for a 3.54㎓ CW signal for... 45

Figure 2-18. Output spectral density of a 10㎒-3G LTE with 8.3-㏈ PAPR before and after pre-... 45

Figure 3-1. Voltage waveform of a PA manipulated using an optimum second harmonic. 50

Figure 3-2. Simplified RF FET model. 51

Figure 3-3. Drain efficiency performance as a function of the knee voltage to supply voltage ratio. 55

Figure 3-4. Input voltage waveform for the different loading condition. 55

Figure 3-5. Input voltage waveforms for different loading conditions. 56

Figure 3-6. Output current waveforms for different loading conditions. 59

Figure 3-7. Peaking effect of current waveform as a function of bi2.(이미지참조) 61

Figure 3-8. Drain current waveform for the different bi2 values.(이미지참조) 62

Figure 3-9. Smith chart of the calculated fundamental and second harmonic reactance curves, and... 64

Figure 3-10. Smith chart of the fundamental and second harmonic reactance curves, and maximum... 65

Figure 3-11. Simulated current waveform for the different second harmonic loading conditions. 66

Figure 3-12. Calculated (a) and (b) simulated RF load line for Class-F-1 and Class-J PA.(이미지참조) 66

Figure 3-13. Smith chart of fundamental and second harmonic impedance curves and constant efficiency... 67

Figure 3-14. Simplified RF FET model including non-linear capacitance 68

Figure 3-15. Measured impedance contour by the harmonic load pull (maintaining an output power of... 69

Figure 3-16. Implemented output matching network 72

Figure 3-17. Simulated (a) and measured (b) S-parameter for proposed output matching network. 73

Figure 3-18. The implemented PAs incorporating the proposed output termination. 73

Figure 3-19. Measured and simulated output power, power gain, drain efficiency, and PAE for a 3.5 ㎓... 74

Figure 3-20. Plotted AM/AM curve as a function of the input modulation signal. 74

Figure 3-21. Spectral density of the average output power (applying same output power back off level of... 75

Figure 4-1. Calculated amplitude distribution of a 10㎒-bandwidth 3G LTE modulated signal with... 80

Figure 4-2. Configuration of a Class-F-1 amplifier and a simplified analytical model of an FET.(이미지참조) 80

Figure 4-3. Normalized nonlinear capacitance versus drain voltage for a GaN device 84

Figure 4-4. Drain efficiency as a function of envelope distribution for different initial capacitance values. 85

Figure 4-5. Simulated voltage and current waveforms for different initial capacitance conditions... 86

Figure 4-6. Load line for different input levels and output envelope signal characteristics. 87

Figure 4-7. Measured power spectral density of PA used different envelope voltage signals. 88

Figure 4-8. Measured output envelope signal characteristic using a non-shaping method, and an optimized... 88

Figure 4-9. Measured power-added efficiencies of PAs versus envelope voltage signals for different... 89

Figure 4-10. Efficiency of the switching stage as a function of switching frequency (a) and the power... 90

Figure 4-11. Simplified schematic of the linear stage using switching stage with different levels. 91

Figure 4-12. Current and voltage values of the switching stage for different quantized levels (the black... 94

Figure 4-13. Simulated and measured efficiencies of an envelope amplifier (RLoad ＝ 8.5Ω)(이미지참조) 95

Figure 4-14. Fully-integrated 3.54㎓ 10W envelope tracking transmitter for a 3G LTE base station. 96

Figure 4-15. Output voltage of the switching stage for different quantized levels 96

Figure 4-16. Output voltage of the switching stage for different quantized levels 97

Figure 4-17. Normalized nonlinear capacitance versus drain voltage for a GaN device 97

Figure 5-1. Highly efficient envelope tracking transmitter. 102

Figure 5-2. Highly efficient envelope tracking transmitter. 103

Figure 5-3. RFPA impedance as function of normalized envelope voltage at given envelope shaping 104

Figure 5-4. Efficiency of an envelope amplifier as a function of a normalized envelope voltage. 104

Figure 5-5. Conventional linear regulator. 105

Figure 5-6. Efficiency of linear regulator versus output voltage back-off. 105

Figure 5-7. Proposed envelope amplifier. 106

Figure 5-8. Equivalent model with respect to the envelope voltage, as described in (9). 107

Figure 5-9. Partial load current under the condition of(9). 108

Figure 5-10. Measured efficiency of dc-dc converter. 108

Figure 5-11. Efficiency of the proposed EA as a function of the envelope voltage compared with that of... 109

Figure 5-12. Load current waveforms through linear regulator blocks. 109

Figure 5-13. Input and output envelope voltage for the proposed EA. 111

Figure 5-14. Instantaneous efficiency for the proposed EA 111

Figure 5-15. Impedance seen by linear regulator as function of normalized envelope voltage. 113

Figure 5-16. Power spectra density of output envelope. 113

Figure 5-17. Fabricated ET transmitter. 114

Figure 5-18. Schematic of the proposed EA with a 2.6 ㎓ 10 W GaN PA. 115

Figure 5-19. Measured s-parameter of the output matching network. 115

Figure 5-20. Measured output power, efficiency, and gain of the implemented PA. 115

Figure 5-21. Measured output power and efficiency with respect to the supply voltage. 116

Figure 5-22. Measured voltage waveform when operating an ET system. 116

Figure 5-23. Measured efficiency of proposed EA. 116

Figure 5-24. Amplitude and phase of output signal and pre-distorted signal. 117

Figure 5-25. Spectra of ET system with and without DPD functionality. 118

Figure 6-1. Current waveforms of the carrier and peaking amplifier as a function of input driven voltage. 122

Figure 6-2. Fundamental current of the carrier and peaking amplifier as a function of input driven voltage. 126

Figure 6-3. Simplified imperfect load modulation effect for the Doherty amplifier (Jell is for a carrier cell... 127

Figure 6-4. Estimated fundamental current of the carrier and peaking amplifier as a function of input... 127

Figure 6-5. Simulation set-up used to identify (19) (for σ＝2). 127

Figure 6-6. Simulated fundamental current of the carrier and peaking amplifier as a function of input... 128

Figure 6-7. Simulated output power and efficiency for different backoff levels as a function of input... 129

Figure 6-8. Simulated load modulation for different backoff levels as a function of input power backoff. 130

Figure 6-9. Previous methods 10 enhance the fundamental current for a peak cell 130

Figure 6-10. Simulated efficiency and output power for an uneven case. 132

Figure 6-11. Simulated efficiency and output power for an asymmetric case. 133

Figure 6-12. Simulated gate voltage and corresponding DC current. 134

Figure 6-13. Transconductance curve as a function of drain voltage. 136

Figure 6-14. Drain envelope voltage waveform. 137

Figure 6-15. Simplified equivalent model for an off-state peaking cell. 137

Figure 6-16. Trajectory of the drain source capacitances (a) and the variation of capacitance as the center... 139

Figure 6-17. Degradation of efficiency and off impedance for different lengths of offset line. 141

Figure 6-18. Calculated (red), simulated (blue), and measured (CW) off impedances for the different... 142

Figure 6-19. Simplified schematic of proposed Doherty amplifier. 142

Figure 6-20. Photograph of fabricated Doherty amplifier. 143

Figure 6-21. Measured DC current of carrier and peaking cells with/without gate envelope modulation as... 143

Figure 6-22. Measured efficiency and output power of a Doherty amplifier with/without gate envelope... 144

Figure 6-23. Measured efficiency for different envelope modulations as a function of output power. 144

Figure 6-24. Measured spectra before/after DPD. 145

Figure 6-25. Measured gate and drain supply voltages. 145

Figure 7-1. Simplified schematic of proposed Doherty PA. 149

Figure 7-2. Simulated gain and PAE versus the output power by sweeping the bias point of the peaking... 150

Figure 7-3. Gain and current versus the output power for Vb2 of 0 and 0.4 V.(이미지참조) 150

Figure 7-4. Reshaped gate voltage of peaking PA Vb2.(이미지참조) 150

Figure 7-5. Proposed Doherty CMOS PA. 152

Figure 7-6. Measured PAE and gain versus the output power. 153

Figure 7-7. Measured spectra density at an output power of 25.2 dBm. 153

Figure 8-1. Schematic of the cascade amplifier stage. 157

Figure 8-2. Measured and simulated drain current and its derivatives versus the gate source voltage (G₂... 157

Figure 8-3. Gain and IMD3 as functions of input power with different VGS1.(이미지참조) 159

Figure 8-4. Drain current versus gate source and drain source voltage. 159

Figure 8-5. Drain current as a function of VGS1 when sweeping VG2(이미지참조) 160

Figure 8-6. G₁ and G₃ as a function of VG2(이미지참조) 161

Figure 8-7. Output power and IMD3 as a function of VG2(이미지참조) 161

Figure 8-8. PAE versus output power with and without the minimum IMD3 tracking. 162

Figure 8-9. The simulated gain and phase response as a function or output power by sweeping VG2(이미지참조) 163

Figure 8-10. The simulated optimum VG2 point and curve fitting shape.(이미지참조) 163

Figure 8-11. Simulated gain/ phase of deviations and IMD3 as a function of temperature(-20/25/85... 165

Figure 8-12. Simulated ACLR as a function of temperature(-20/25/85 degree) 165

Figure 8-13. Schematic of envelope amplifier prototype. 165

Figure 8-14. Measured efficiency of envelope amplifier with 3.9 Ohm load. 166

Figure 8-15. Output load of proposed CMOS RF PA. 167

Figure 8-16. Simulated fundamental, second and third harmonic impedances from RLOAD and (b) drain...(이미지참조) 167

Figure 8-17. Photograph of CMOS PA and OPA. 168

Figure 8-18. Photograph of the measurement setup. 168

Figure 8-19. Schematic of proposed CMOS ET transmitter. 169

Figure 8-20. Measured output power versus input power by sweeping VG2 from 2.4 to 3.6 V.(이미지참조) 170

Figure 8-21. Measured gain and PAE as a function of output power by sweeping VG2 from 2.4 to 3.6 V.(이미지참조) 170

Figure 8-22. Measured PAE as a function of supply voltage, VET(이미지참조) 170

Figure 8-23. Measured IMD3 as a function of input power by sweeping VG2 from 2.4 to 3.6 V(이미지참조) 172

Figure 8-24. Measured trajectory of IMD3 for w/ and w/o ET operation. 173

Figure 8-25. Measured EVM and ACLR for different VG2 under ET mode.(이미지참조) 173

Figure 8-26. Measured spectra for different VG2 under ET mode.(이미지참조) 174