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Title Page

초록

Abstract

Contents

Chapter 1. Introduction 9

1.1. The Requirements of High Performance and High Bandwidth System 9

1.2. Introduction to High Bandwidth Memory (HBM) 10

1.3. Signal Integrity (SI) Issues at the TSV Array in HBM 12

1.4. Necessities of Optimal Through Silicon Via (TSV) Array Design through Pattern Revision 13

1.5. The Conventional TSV Array Design Method for HBM 14

1.6. Introduction to Reinforcement Learning (RL) 15

1.7. Previous Works 16

1.8. Research Motivations and Objectives 17

Chapter 2. Proposal of Deep Reinforcement Learning-based Through Silicon Via (TSV) Array Design Optimization Method 18

2.1. Proposed RL-based TSV Array Optimization Method considering SI 18

2.2. Hyperparameters of Markov Decision Process for the Proposed Method 19

2.2.1. State: Representation of TSV Array as a Matrix 19

2.2.2. Action: Switching TSVs for Design Revision considering SI 20

2.2.3. Reward: The Eye Height of the TSV Channel 21

2.3. Eye Diagram Estimation Method for Reward 22

2.3.1. Equivalent Circuit Modeling of Multi-signal and Multi-ground TSVs 22

2.3.2. Eye Diagram Estimation using Equivalent Circuit Model 24

2.4. Learning Procedure of the Proposed Method 25

2.5. Optimal TSV Array Design Procedure 26

2.6. Key Features and the Advantage of the Proposed Method 27

Chapter 3. Verification of the Proposed Method by Comparison with Full Search Method 27

3.1. The Physical Dimension and the simulation setup of the Target Through Silicon Via (TSV) Array for Verification 27

3.2. Hyperparameters of the Proposed Method 29

3.3. Training Loss and Average Reward of the Proposed Method 30

3.4. Optimal TSV Array Design Procedure with Trained Agent 31

3.4.1. Optimal Design and Analysis of Case 1 31

3.4.2. Optimal Design and Analysis of Case 2 34

3.5. Comparison of the Consuming Time and Performance between Proposed method and Full Search Optimization 37

Chapter 4. Application of the Proposed Method for High Bandwidth Memory (HBM) TSV Array 38

4.1. Target Application for the Proposed Method: 1 Byte of HBM TSV DQ Channel 38

4.2. The Physical Dimension of the Target Through Silicon Via (TSV) Array in HBM 38

4.3. Hyperparameters 39

4.4. Optimal TSV Array Design Procedure with Trained Agent at HBM 40

Chapter 5. Discussions and Conclusion 42

5.1. The Limitations of the Proposed Method 42

5.2. Further Work: Optimization using Policy-based RL Methods 43

5.3. Conclusion 43

Bibliography 44

Curriculum Vitae in Korean 46

List of Tables

Table 1. The physical dimension of the TSV array 28

Table 2. Parameters of target TSV array channel 28

Table 3. Hyperparameters of the proposed method 29

Table 4. Comparison of eye height between the proposed method and full search method at case 1 31

Table 5. Comparison of eye height between the proposed method and full search method at case 2 34

Table 6. Comparison of the proposed method and full search method 37

Table 7. Hyperparameters for 4x4 TSV array optimization at HBM 39

Table 8. Comparison of eye height between the proposed method and full search method at 4x4 TSV array 40

List of Figures

Figure 1. The requirement of high performance and high bandwidth system 9

Figure 2. The trend of memory bandwidth and the neural network training requirement 10

Figure 3. HBM mounted on graphic modules and the data bandwidth specification of HBM 2E 10

Figure 4. Key features of HBM 11

Figure 5. TSV and TSV array in HBM 11

Figure 6. Signal integrity issues at the TSV array at HBM 12

Figure 7. Design methods for TSV array at HBM 13

Figure 8. Necessities of optimal through silicon via (TSV) array design through pattern revision 14

Figure 9. The conventional TSV array design method for HBM 15

Figure 10. The concept of reinforcement learning (RL) 15

Figure 11. The concept of deep reinforcement learning (DRL) 16

Figure 12. Previous work 1: TSV-aware analytical placement for 3-D IC designs 16

Figure 13. Previous work 2: Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC 17

Figure 14. The concept of RL-based TSV array optimization considering SI 18

Figure 15. Schematic diagram of the deep q learning-based proposed method 19

Figure 16. State: Representation of TSV array as a matrix 20

Figure 17. Action: Switching TSVs 20

Figure 18. Reward: Eye height of the worst TSV channel 21

Figure 19. Eye diagram estimation method for reward 22

Figure 20. Inductance modeling of multi-signal and multi-ground TSVs 22

Figure 21. Capacitance and conductance modeling of multi-signal and multi-ground TSVs 23

Figure 22. Flow chart of eye diagram estimation from the equivalent circuit model 24

Figure 23. Learning Procedure of the Proposed Method 25

Figure 24. Epsilon-greedy policy process 26

Figure 25. Overall Steps of the Optimal TSV Array Design Procedure 26

Figure 26. The physical dimension of the target TSV array for verification 27

Figure 27. Target TSV array channel eye-diagram simulation setup 28

Figure 28. Training Loss of the Proposed Method 30

Figure 29. Average Reward of the Proposed Method 30

Figure 30. Optimal TSV array design procedure with a trained agent of case1 31

Figure 31. Eye diagram of optimal TSV array at case 1 32

Figure 32. Par-end crosstalk (FEXT) of each state at case 1 32

Figure 33. FEXT analysis of the design procedure of TSV array using the proposed method at case 1 33

Figure 34. Optimal TSV array design procedure with a trained agent of case2 34

Figure 35. Optimal TSV array design procedure with a trained agent at case2 35

Figure 36. Far-end crosstalk (FEXT) of each state at case 2 35

Figure 37. FEXT analysis of the design procedure of TSV array using the proposed method at case 2 36

Figure 38. The concept of the proposed method using RL the full search method 37

Figure 39. The target application for the proposed method: 1 Byte of HBM TSV DQ channel 38

Figure 40. Initial design and target TSV array dimension 39

Figure 41. Optimal 4x4 TSV array design procedure with the trained agent at HBM 40

Figure 42. Eye diagram of optimal 4x4 TSV array at HBM 41

Figure 43. Far-end crosstalk (FEXT) of each state at 4x4 TSV array 41

Figure 44. Limitations of the proposed value-based RL method 42

Figure 45. Advantage of the policy-based RL method 43

초록보기

본 논문에서는 최초로 심층 강화학습을 이용한 고대역폭 메모리(HBM)의 실리콘 관통 전극 (TSV) 배열 설계 최적화 방법을 제안하였다. 제안된 방법을 통해 훈련된 에이전트는 TSV 채널의 아이-높이를 한 번에 극대화하는 최적의 TSV 어레이를 제공할 수 있다. 신호 무결성 (SI) 을 고려하여 TSV 어레이를 최적화하고 에이전트를 훈련하기 위한 마르코프 결정 과정의 요소들을 SI를 고려하여 정의하였다. 검증을 위해 제안된 방법을 소요 시간과 성능 관점에서 3x3 TSV 어레이에서 전체 검색 알고리즘과 비교하였다. 검증된 방법을 HBM의 1바이트 신호 채널을 포함하는 4x4 TSV 어레이 최적 설계에 적용하였다.

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