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Title Page

Abstract

Contents

Nomenclature 12

Chapter Ⅰ. Overview 14

Chapter Ⅱ. Introduction 15

2.1. Introduction of Graphene 15

2.1.1. Graphene characteristic 15

2.1.2. Physical quantity of graphene 21

2.2. Raman spectroscopy 22

2.2.1. Raman peak of graphene and orientation 24

2.2.2. Raman characterization of graphene 27

2.3. Introduction of Photolithography 28

2.4. Introduction of Reactive Ion Etching 30

2.5. Introduction of Aluminum oxide 32

2.5.1. Aluminum oxide 32

2.5.2. Trap states oxide layers 32

2.6. Graphene Field-Effect Transistor 34

2.6.1. Electric characteristic of Graphene Field-Effect Transistor 34

2.6.2. Minimum conductance 34

2.6.3. Field-effect mobility 35

2.6.4. Sweep hysteresis 36

2.7. NAND flash memory 37

2.7.1. Floating gate 37

2.7.2. ONO structure 37

Chapter Ⅲ. Approaches & Measurement 39

3.1. Fabrication 39

3.2. Results 43

Chapter Ⅳ. Summary & Conclusion 50

References 51

List of Figures

Figure 1. Lattice vector of graphene 17

Figure 2. Band diagram of graphene 18

Figure 3. Graphene lattice and structure 19

Figure 4. Synthesize of graphene 19

Figure 5. Exfoliation of graphene 20

Figure 6. Schematic of Raman spectrometer 23

Figure 7. Schematic of Raman scattering 23

Figure 8. Graphene Raman peaks 25

Figure 9. Vibrational mode 25

Figure 10. Schematic of Raman scattering in graphene 26

Figure 11. Schematic of Photolithography 29

Figure 12. Schematic of Reactive Ion Etching 31

Figure 13. Energy levels 33

Figure 14. Floating gate and ONO structure NAND flash memory 38

Figure 15. Schematic of Charge Trapping Nitride 38

Figure 16. Fabrication of GFET 41

Figure 17. Back-gate probe contact 42

Figure 18. Graphene Coverage 45

Figure 19. Raman shifts and FWHM of graphene on substrates 46

Figure 20. Transfer curve 47

Figure 21. Retention of device 48

Figure 22. Schematic of charge trapping memory effect of Al₂O₃/SiO₂ substrate 49

초록보기

 Graphene, characterized by its singular plane of carbon atoms forming a hexagonal lattice, has become a focal point due to its unique electronic, mechanical, and thermal attributes.

In this study, we investigated the effects of an Al₂O₃ layer deposited on a SiO₂ gate insulator of a conventional back-gated graphene field effect transistor (GFET). The graphene layer is procured through chemical vapor deposition on copper substrates (sourced from Graphenea) and subsequently placed onto Si-wafer with a SiO₂ or Al₂O₃/SiO₂ surface layer via a semi-dry transfer technique. The Al₂O₃ layer has a thickness of 12nm, and the SiO₂ layer is 100nm thick.

Through Raman spectroscopy, we discussed the strain and concentration of doping in the graphene channel after transfer. The 2D peak values for graphene transferred on SiO₂ and Al₂O₃/SiO₂ are approximately 2681 cm-1 and 2673 cm-1 in the same sequence, and G peaks are detected around 1591 cm-1 and 1585 cm-1 correspondingly. These peaks, exhibiting a blue shift relative to inherent graphene, validate p-type doping on both substrates, with graphene on SiO₂ substrate anticipated to possess a heightened hole concentration. The graphene channel is patterned using photolithography, following the deposition of Au/Ti electrodes (with dimensions of 50nm/20nm) positioned at the terminal edges of the channel, which serve as source and drain electrode.

Pronounced hysteresis in the transfer curves, displaying drain-to-source current (IDS) in relation to gate voltage (Vg), is discerned for graphene on both SiO₂ and Al₂O₃/SiO₂ insulator substrates. This phenomenon is believed to originate from charge trapping within the insulating layers, which affects the carrier behavior in the graphene channel.

In our memory retention tests, triangular pulses of +60V and -60V were applied to the Vg. Immediately after each pulse, with Vg reset to 0V, the IDS was recorded over a 60,000-second duration.

A pronounced memory influence is evident in GFETs incorporating the Al₂O₃/SiO₂ insulator stack as opposed to the singular SiO₂ insulator. Conclusively, the findings advocate that the GFET with a rear-gate setup complemented by an Al₂O₃/SiO₂ insulator layer can serve as a viable substitute to the conventional Oxide-Nitride-Oxide memory structure.

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