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Title Page 2

ABSTRACT 5

Contents 8

List of Abbreviations 17

CHAPTER 1. Introduction 20

CHAPTER 2. Bio-potential Monitoring System 22

Chapter 2.1. Bio-potential Monitoring on Wearable Devices 22

Chapter 2.2. Bio-potential Characteristics 25

Chapter 2.3. Electrode Sensors for Bio-potential Monitoring 27

2.3.1. Electrolyte-Electrode Interface 27

2.3.2. Types of Non-Invasive Body Surface Electrode 28

Chapter 2.4. Chapter Summary 29

CHAPTER 3. MOS Device Review and Noise Cancellation Techniques 30

Chapter 3.1. Basic Metal-oxide-semiconductor (MOS) Device Review 30

3.1.1. EKV Model Review 30

3.1.2. Noise of MOS Transistor 34

3.1.3. gm/ID Design Methodology and Noise Efficiency Factor (NEF)[이미지참조] 36

Chapter 3.2. Noise Cancellation Techniques 41

3.2.1. Thermal Noise in Sample and Hold Circuits 41

3.2.2. Thermal Noise Reduction Techniques 44

3.2.3. 1/f Noise Reduction Techniques 49

Chapter 3.3. Chapter Summary 59

CHAPTER 4. Capacitively-coupled Chopper Instrumentation Amplifier (CCIA) 60

Chapter 4.1. Basic Working Principles and Design Challenges 60

4.1.1. Basic Topology 60

4.1.2. Design Challenges 63

Chapter 4.2. Capacitively-coupled Chopper Instrumentation Amplifier (CCIA) Design 69

4.2.1. DC Servo Loop (DSL) 69

4.2.2. Ripple Rejection Loop (RRL) 73

4.2.3. Positive Feedback Loop (PFL) 75

Chapter 4.3. Trade-off for Designing the CCIA for Bio-potential Monitoring Applications 78

Chapter 4.4. Chapter Summary 79

CHAPTER 5. CCIA Design for Real-Time Depth of Anesthesia Monitoring System 80

Chapter 5.1. Applications: Depth of Anesthesia Monitoring System 80

Chapter 5.2. Proposed EEG AFE Architecture 83

5.2.1. Overall Architecture 83

5.2.2. Circuit Implementation 85

5.2.3. Single-Slope Assisted DSL 87

Chapter 5.3. Experimental Results 91

5.3.1. Electrical Measurement of EEG AFE 91

5.3.2. In vivo and In vitro Measurement 92

5.3.3. System Comparisons 94

Chapter 5.4. Chapter Summary 95

CHAPTER 6. CCIA Design with Dual Positive Feedback Loop (DPFL) 96

Chapter 6.1. Introduction: External Parasitic Capacitance and Total Input Impedance 96

Chapter 6.2. Conventional Positive Feedback Loop 98

6.2.1. Conventional PFL with Cp-EXT[이미지참조] 98

6.2.2. Conventional PFL with DSL Operation 99

Chapter 6.3. Previous Works for Input Impedance Boosting 101

Chapter 6.4. Proposed CCIA with Dual Positive Feedback Loop (DPFL) 104

6.4.1. Operational Principles of the DPFL 104

6.4.2. Circuit Implementation 107

6.4.3. Auto-Calibration Scheme 111

6.4.4. Noise Analysis 114

Chapter 6.5. Experimental Results 117

6.5.1. Electrical Measurement of Proposed AFE 117

6.5.2. Total Input Impedance Measurement 119

6.5.3. In vivo Measurement 121

6.5.4. System Comparisons 122

Chapter 6.6. Chapter Summary 123

CHAPTER 7. CCIA Design with Common Mode Interference (CMI) Follower 124

Chapter 7.1. Introduction: Common Mode Interference (CMI) through Human Body 124

7.1.1. Three Electrodes Model 124

7.1.2. Two Electrodes Model 126

7.1.3. Total Common Mode Rejection Ratio (T-CMRR) 128

Chapter 7.2. Previous Works for CMI Rejection and High T-CMRR 130

7.2.1. Three Electrodes System 130

7.2.2. Two Electrodes System 135

Chapter 7.3. Proposed CCIA with CMI Follower 141

7.3.1. Operational Principles of CMI Follower 141

7.3.2. Operational Principles of Common Mode Adaptive Current Reuse OTA (CMA-CR-OTA) 150

7.3.3. Circuit Implementation 156

Chapter 7.4. Experimental Results 160

7.4.1. Measurement Setup 160

7.4.2. Electrical Measurement Results of Proposed AFE 161

7.4.3. Measurement Results of CMA-CR-OTA 163

7.4.4. Measurement Results of CMI Follower 164

7.4.5. In vivo Measurement Results 167

7.4.6. System Comparisons 170

Chapter 7.5. Chapter Summary 171

CHAPTER 8. Conclusion and Limitations 172

References 173

CURRICULUM VITAE 184

List of Tables 16

Table Ⅰ. Two international standards for clinical EEG measurement 25

Table Ⅱ. Conditions for different mode of operations 33

Table Ⅲ. Drain current equations for different mode of operations 33

Table Ⅳ. Drain current equations for different mode of operations 34

Table Ⅴ. Thermal noise conductance and drain current PSD in weak and strong inversion... 35

Table Ⅵ. Total noise summarize with respect to noise sources in active reset scheme 47

Table Ⅶ. Comparisons of EEG AFE with state-of-the art 94

Table Ⅷ. Comparisons of proposed CCIA with state-of-the art 122

Table Ⅸ. Comparisons of proposed AFE with state-of-the art 170

List of Figures 11

Fig. 1. Challenges bio-potential AFE faces with and trade-off relationship 20

Fig. 2.1.1. A variety of wearable sensors to monitor the bio-potential signals 22

Fig. 2.1.2. One example of the wearable ECG monitoring system and market growth of wearable.. 23

Fig. 2.2.1. Signal amplitude of the bio-potential signals with respect to the frequency and.. 25

Fig. 2.3.1. Equivalent electrical models of (a) wet/gel electrode, (b) dry electrode and (c) non-... 28

Fig. 3.1.1. Ideal structure of a NMOS transistor 30

Fig. 3.1.2. Inverted charge on channel and channel potential 31

Fig. 3.1.3. IC vs Normalized VGS-VT with respect to operating regions[이미지참조] 36

Fig. 3.1.4. The gm, gm/IDS, IDS, and fT vs IC in weak and strong inversion[이미지참조] 37

Fig. 3.1.5. gm/IDS·nUT vs IC with respect to operating regions[이미지참조] 38

Fig. 3.1.6. The NEF of fully differential inputs pair operated in weak and strong inversions 39

Fig. 3.1.7. The NEF of three different OTA structures 40

Fig. 3.2.1. Simplified sample and hold circuits and its noise in time-domain 41

Fig. 3.2.2. Noise floor with different switch on resistance 42

Fig. 3.2.3. (a) 3T image sensor pixel and (b) stray-insensitive switched capacitor (SC) integrator 42

Fig. 3.2.4. Noise models of stray-insensitive SC integrator during each phase 43

Fig. 3.2.5. Gate voltage difference between hard reset and soft reset 44

Fig. 3.2.6. (a) Pixel schematic with active reset and (b) small signal noise model of reset phase 46

Fig. 3.2.7. (a) Cₑq vs Rsw with respect to CFB and (b) corresponding settling time constant[이미지참조] 47

Fig. 3.2.8. Operational principles of kT/C noise cancellation technique 48

Fig. 3.2.9. (a) Simplified block schematic of auto-zeroing and (b) low frequency noise Modeling 49

Fig. 3.2.10. Noise transfer function of the auto-zeroing including baseband and folding 51

Fig. 3.2.11. Simplified noise folding diagram with ideally low pass filtered white noise, and its... 51

Fig. 3.2.12. Simplified noise folding diagram with 1st order low pass filtered white noise 52

Fig. 3.2.13. (a) Noise components generated by auto-zeroing process for white noise and (b)... 53

Fig. 3.2.14. (a) Noise components generated by auto-zeroing process for l/f noise and (b) overall... 53

Fig. 3.2.15. Simplified chopper stabilized amplifier and its operational principle 54

Fig. 3.2.16. Block diagram of chopping technique 55

Fig. 3.2.17. Modulated output noise with 1st order low pass filtered white noise 56

Fig. 3.2.18. (a) Normalized PSD of SY(f) with low pass filtered 1/f noise and (b) with respect to...[이미지참조] 57

Fig. 3.2.19. Normalized PSD of modulated 1/f noise with respect to different 1/f corner... 58

Fig. 4.1.1. Chopping technique with capacitive negative feedback topology 60

Fig. 4.1.2. Chopping technique with capacitive negative feedback topology 61

Fig. 4.1.3. Noise modeling of chopping switches with input parasitic capacitance Cₚ 62

Fig. 4.1.4. Noise modeling of chopping switches with input parasitic capacitance Cₚ 62

Fig. 4.1.5. Input referred noise comparison of two different chopping switch positions: (a)... 63

Fig. 4.1.6. DC-coupling characteristics of the CCIA 64

Fig. 4.1.7. Simplified chopping ripple generation mechanism 65

Fig. 4.1.8. Dry-electrode model and input impedance of the instrumentation amplifier 66

Fig. 4.1.9. DM input impedance model of the CCIA 66

Fig. 4.1.10. DM input impedance of the CCIA with 30-pF, CIN and 5-kHz, Fcₕₒₚ[이미지참조] 67

Fig. 4.1.11. CM input impedance model of the CCIA 68

Fig. 4.2.1. Simplified block diagram of DC Servo loop 69

Fig. 4.2.2. (a) Active RC integrator for the DSL and (b) resistor candidates 70

Fig. 4.2.3. (a) Parasitic switched capacitor resistance effect and (b) multi-rate duty-cycled... 72

Fig. 4.2.4. Active gm-C integrator with resistor division attenuator for DSL 72

Fig. 4.2.5. Continuous time current feedback RRL 73

Fig. 4.2.6. Passive ripple rejection by blocking the Vₒffₛₑₜ through CDC[이미지참조] 74

Fig. 4.2.7. Digital assisted offset calibration with passive ripple rejection 75

Fig. 4.2.8. Input current drawn by the CIN and CP-IN[이미지참조] 76

Fig. 4.2.9. Positive feedback loop (PFL) and its current flowing 76

Fig. 5.1.1. Conceptual diagram of novel DoA index EEGMAC 81

Fig. 5.1.2. Overall architecture of DoA monitoring system with EEG AFE and Raspberry Pi 3 for... 82

Fig. 5.2.1. Simplified noise model of analog DSL in the CCIA 83

Fig. 5.2.2. (a) DSL with chopping and DSL with GNNCL loop for suppressing DSL's noise... 84

Fig. 5.2.3. EEG AFE including the CCIA with simplified SS-DSL, PGA, and SAR ADC 85

Fig. 5.2.4. Detailed schematic of OTA designs including Gₘ₁, Gₘ₂ and Gₘ₃ in Fig.5.2.3 86

Fig. 5.2.5. Detailed schematic of the Gm₅ in Fig.5.2.3, and its CMFB circuit 86

Fig. 5.2.6. Detailed schematic of the SS-DSL in the CCIA 88

Fig. 5.2.7. Detailed schematic of logic block in SS-DSL 89

Fig. 5.2.8. Operational principles of SS-DSL with two different EDO polarity 89

Fig. 5.3.1. (a) Proposed DoA system with EEG recording IC and Raspberry Pi3 and (b)... 91

Fig. 5.3.2. (a) Measured frequency response and (b) IRN with or without chopping 92

Fig. 5.3.3. (a) In vivo EEG measurement with a male candidate without sedation and (b)... 92

Fig. 5.3.4. In vitro measurement results with pre-recorded EEG combined with 70 mV EDO step 93

Fig. 6.1.1. Smart glasses where EOG sensor integrated 96

Fig. 6.1.2. Total input impedance (T-ZIN) with Cp-EXT and IC-ZIN[이미지참조] 97

Fig. 6.2.1. T-ZIN and IC-ZIN in the CCIA structure with conventional PFL[이미지참조] 98

Fig. 6.2.2. The CCIA structure with the PFL and DSL modeled as the first order ideal integrator 100

Fig. 6.3.1. Input impedance boosting techniques of PFL with two different calibration methods:... 101

Fig. 6.3.2. Input impedance boosting techniques: (a) PFL with varactor [94] and (b) pre-charging... 102

Fig. 6.4.1. Proposed DPFL consisting of internal PFL with APF and external PFL[이미지참조] 104

Fig. 6.4.2. Simulated T-ZIN with the conventional PFL (red line) and DPFL (blue line)[이미지참조] 105

Fig. 6.4.3. Simulated frequency response of the T-ZIN with the DPFL and DSL operations[이미지참조] 106

Fig. 6.4.4. Overall CCIA architecture with DPFL and auto-calibration scheme 107

Fig. 6.4.5. Detailed schematics for A₁: (a) self-biased current reuse OTA for first stage and (b)... 108

Fig. 6.4.6. Detailed schematics for (a) APF and (b) signal generator (SG)[이미지참조] 108

Fig. 6.4.7. Layout of the unit capacitors for both CPF and CEPF and its unit capacitance with... 110

Fig. 6.4.8. Layout of the 7-b, CPF and 8-b CEPF[이미지참조] 110

Fig. 6.4.9. Simplified auto-calibration plan for internal PFL 111

Fig. 6.4.10. Simplified schematic for calibration logic and comparator 113

Fig. 6.4.11. Simplified timing diagram of the auto-calibration process 113

Fig. 6.4.12. Equivalent noise model of proposed CCIA interfacing with dry-electrode impedance 114

Fig. 6.5.1. (a) Fabricated chip micrograph and (b) power breakdown 117

Fig. 6.5.2. (a) Measured frequency response of proposed AFE and (b) measured IRN with... 117

Fig. 6.5.3. Measured THD with respect to input voltages with or without DPFL calibration 118

Fig. 6.5.4. Measurement set up for measuring T-ZIN[이미지참조] 119

Fig. 6.5.5. Measured T-ZIN with (a) manually calibrated and (b) auto-calibrated CPF and CEPF[이미지참조] 120

Fig. 6.5.6. Measured T-ZIN of six prototype samples 50Hz with the CP-EXT of 25 pF[이미지참조] 121

Fig. 6.5.7. In vivo testing to validate prototype AFE: (a) measured ECG waveform, (b) measured... 121

Fig. 7.1.1. Electrical modeling including human body and ECG AFE with three electrodes 124

Fig. 7.1.2. Electrical modeling including human body and ECG AFE with two electrodes 126

Fig. 7.1.3. Large CMI coupling with issue with ESD operation 127

Fig. 7.1.4. Electrical model for the analysis of T-CMRR 128

Fig. 7.2.1. Electrical model for the analysis of the DRL technique 130

Fig. 7.2.2. The CCIA architecture with CMCL 132

Fig. 7.2.3. (a) Common Mode Replication (CM-REP) architecture and detailed schematic of Gₘ₁... 133

Fig. 7.2.4. (a) Simplified common mode charge pump (CMCP) schematic and (b) operational... 135

Fig. 7.2.5. Simplified CMCP with T-CMRR enhancing loop 137

Fig. 7.2.6. Simplified common mode averaging unit (CMAU) 138

Fig. 7.2.7. Simplified pseudo-RLD with adaptive biasing circuit 140

Fig. 7.3.1. CMI coupling analysis in two-electrode system with the CSEN on the input nodes of IA[이미지참조] 141

Fig. 7.3.2. CMI coupling analysis in two-electrode system with the CSEN and CRES[이미지참조] 142

Fig. 7.3.3. Simplified proposed CMI Follower schematic 143

Fig. 7.3.4. Small signal analysis model of the proposed CMI Follower 144

Fig. 7.3.5. Simulated VIN-CM, VACMI-OUT-C, Chip GND, and DM Output with CMI Follower[이미지참조] 146

Fig. 7.3.6. VCMI Tolerance with respect to CGND and CSEN[이미지참조] 146

Fig. 7.3.7. (a) CMI Follower with electrode mismatch and (b) simplified ZIN-CM of CMI Follower...[이미지참조] 147

Fig. 7.3.8. Simulated T-CMRR with ∆ZEL and various CGND[이미지참조] 148

Fig. 7.3.9. (a) Distorted VIN-CM with limited output swing of ACMI and (b) simulation result with...[이미지참조] 150

Fig. 7.3.10. Frequency response simulation of self-biased current reuse OTA 151

Fig. 7.3.11. Replica biasing circuit for enhancing PSRR 152

Fig. 7.3.12. Detailed schematic of proposed Common mode adaptive CR OTA (CMA-CR-OTA) 153

Fig. 7.3.13. Simulated ID, Gₘ and A₀ of the self-biased CR-OTA and proposed CMA-CR-OTA 154

Fig. 7.3.14. CMI coupling with CMA-CR-OTA in negative feedback 155

Fig. 7.3.15. Overall architecture of proposed CCIA with CMI Follower and CMA-CR-OTA 156

Fig. 7.3.16. Detailed Schematic of proposed CMI Follower and ripple from RCMI[이미지참조] 157

Fig. 7.3.17. Detailed Schematic of proposed CMI Follower and ripple from RCMI[이미지참조] 158

Fig. 7.3.18. T-ZIN degradation due to CSEN and external PFL to compensate it[이미지참조] 159

Fig. 7.4.1. (a) Measurement setup for generating DM and CM input below and (b) above the... 160

Fig. 7.4.2. Measurement board set up: front (a) and back (b) 161

Fig. 7.4.3. (a) Chip micrograph of proposed AFE and (b) power breakdown of AFE 161

Fig. 7.4.4. Measured frequency response of the proposed AFE 162

Fig. 7.4.5. (a) Measured IRN of the proposed AFE with or without CMI Follower and (b)... 162

Fig. 7.4.6. Measured output voltage and power of CMA-CR-OTA and conventional self-biased... 163

Fig. 7.4.7. Measured SNDR with respect to CMI coupling 164

Fig. 7.4.8. Theoretical T-CMRR and measured T-CMRR with respect to electrode mismatches 165

Fig. 7.4.9. Settling experiments: measurement of settling time of CMI Follower from off state to... 166

Fig. 7.4.10. ECG Measurement using two dry electrodes while the subject's foot is in contact... 167

Fig. 7.4.11. ECG Measurement using two different electrodes: one is wet electrode and the other... 168

Fig. 7.4.12. Single arm ECG measurement setup with two-electrodes and measured single arm... 168

Fig. 7.4.13. EEG measurement results including EEG spectrogram, PSD, time domain and... 169

초록보기

 As physiological data garnered by bio-potential recording systems, such as electroencephalograms(EEG), electrocardiogram (ECG), electrooculogram(EOG), and electromyogram(EMG) has been getting popular being crucial for people's daily life over past decades. More recently, wearable devices such as smart glasses and smartwatches have incorporated bio-potential recording capabilities. As a result, electronics which interface with passive sensor such as electrodes have become more crucial blocks. Especially, various types of passive sensors such as dry-electrode or non-contact electrode have been adopted for providing better user experience and durability. Therefore, the analog front-end(AFE) which is the initial block interfacing with these sensors, has been developed.

The primary function of the AFE is amplifying the small bio-potential signals so that relatively low-resolution analog to digital converter (ADC) can quantize them more energy-efficiently. As a result, the AFE should have low noise, large dynamic range, high input impedance, and low power consumption as well. However, traditional AFE designs still face trade-offs between these requirements. For instance, employing a conventional capacitive negative feedback amplifier for the AFE can improve the noise performance with a larger input capacitor, while reducing the input impedance. Consequently, extensive novel structures for AFE have been developed over the past 20 years to address these trade-offs.

Especially, the two-electrode measurement method has recently seen a resurgence due to its good user comfort and low electrode fabrication costs. However, eliminating the biasing electrode results in significant common mode interference (CMI), exceeding the supply voltage, which demands an extremely high common mode rejection ratio (CMRR) of the AFE. This challenge is compounded by the recent trend towards implementing AFEs with lower supply voltages to accommodate smaller batteries or energy harvesting system.

In this thesis, three main features have been introduced. First, energy efficient DC dynamic range enhanced AFE is designed with analog digital mixed mode DC servo loop to tolerate large electrode dc offset (EDO) up to ±380㎹ for the depth of anesthesia (DoA) monitoring. Fabricated in 110-㎚ CMOS process, the prototype AFE consumes 4.33 ㎼ per channel and has the input-referred noise of 0.29 ㎶rms within the signal bandwidth such as 0.5 to 100 ㎐ with the noise efficiency factor of 2.2.

Second, a capacitively-coupled chopper instrument amplifier(CCIA) with auto-calibrated dual positive feedback loop(DPFL) is proposed in this thesis. The proposed AFE with the DPFL does not only prevent total input impedance degradation by undetermined external and internal parasitic capacitances but also achieves good noise efficiency. The DPFL consists of a conventional internal positive feedback loop with an attenuator for enhancing calibration resolution and an external positive feedback loop outside of the input chopper to compensate for a large external parasitic capacitance boosting the total input impedance significantly. To precisely determine the feedback factor of the DPFL in accordance with parasitic capacitors, an on-chip foreground calibration is also implemented in this work. Fabricated in a 110-㎚ CMOS process, the prototype AFE consumes 3.8.㎼ per channel and has input-referred noise of 0.36 ㎶rms from 0.5 to 300㎐ with noise efficiency factor of 1.54. The proposed AFE achieves high-input impedance of 15GΩ at 10㎐ and 2GΩ at 50㎐.

Lastly, CCIA-based AFE for two-electrode bio-potential monitoring system has been developed with large CMI tolerance up to 133VPP. In this work, CMI Follower has been adopted for providing common mode low impedance path while chip ground isolated from earth ground. With chip ground isolation and common mode low impedance path, proposed AFE achieves 133 VPP CMI tolerance while consuming relatively low power, 4.6㎼ per channel and having good noise performance of 0.34㎶rms from 0.5 to 100㎐. The total CMRR(T-CMRR) has been measured as 102㏈ with 10 ㏀ mismatch at 60㎐ and fast settling feature has been validated below 0.2s.

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