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This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, which uses a down literal circuit (DLC) with a floating-gate metal-oxide semiconductor transistor (FGMOS) based on a neuron model. The detection circuit is designed and simulated in a 3.3 V, 0.35 μm standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, the pixel layout size can be reduced and the image resolution can be improved.

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권호기사 목록 테이블로 기사명, 저자명, 페이지, 원문, 기사목차 순으로 되어있습니다.
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참고문헌 (6건) : 자료제공( 네이버학술정보 )

참고문헌 목록에 대한 테이블로 번호, 참고문헌, 국회도서관 소장유무로 구성되어 있습니다.
번호 참고문헌 국회도서관 소장유무
1 Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs 네이버 미소장
2 A CMOS integrated capacitive fingerprint sensor with 32-bit RISC microcontroller 네이버 미소장
3 Design and implementation of a capacitive fingerprint sensor circuit in CMOS technology 네이버 미소장
4 M. Nakahodo, C. Yamada, and Y. Nagata, (2007),“Threshold gate with hysteresis using neuron MOS,” Proceedings of the 7th WSEAS International Conference on Systems Theory and Scientific Computation, Athens, Greece, pp. 157-162. 미소장
5 Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System 네이버 미소장
6 S. I. Han, H. K. Lee, J. H. Hwang, and H. S. Kim, (2003),“A study on the design of binary to quaternary converter,” Proceedings of the Institute of Electronics Engineers - System and Control, 40(3), pp. 60-70. 미소장