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22대 대한민국 국회 국회정보길라잡이 국회의원검색
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초록보기

In this paper, design methodologies suitable for implementing digital systems at various processes are suggested. Important issues such as Multi Corner Multi Mode, Hierarchical Design, adoption of CCS model, and changes in design flow must be considered for ultra-fine processes. The Cortex-M0 SoC Platform is implemented, taking into account theses important issues, and the results using various digital libraries are compared.

All implemented platforms meet specifications and operate normally with both hardware and software. The fastest clock cycle that can be synthesized is 4ns for Samsung 28nm process.

권호기사

권호기사 목록 테이블로 기사명, 저자명, 페이지, 원문, 기사목차 순으로 되어있습니다.
기사명 저자명 페이지 원문 목차
Design of 1:1 transformer based 2-stage differential low-noise amplifier for W-band radar Jae-Eun Lee, Choul-Young Kim p. [1-5]

Ka-band CMOS power amplifier with self-biasing-resistor Younseok Han, Gwanghyeon Jeong p. [1-6]

Design of a 128x128 ROIC array for development of uncooled 2.6 μm-wavelength SWIR imaging camera Min-Jun Park, Ji-Yeon Jeon, Sang-Jun Lee, Hyeon-June Kim p. [1-6]

(A) current-mode VCSEL driver for short-range LiDAR sensors in 180-nm CMOS Xinyue Zhang, Yeojin Chon, Shinhae Choi, Sung Min Park p. [1-5]

(A) 6.4Gbit/s 3-tap high-speed IO FIR driver with LMS adaptation algorithm in 65nm CMOS Chankyu Yu, Seungwoo Shim, Taehyoun Oh p. [1-7]

(An) 8G Hz SST transmitter with adjustable FIR and pre-emphasis logic in 65nm CMOS Zhang Yidan, Tae wook Kim p. [1-6]

Beamforming transmitter IC for far-field wireless charging Seok-Jae Hur, Ji-Hun Kim, Min-su Park, Ho-won Kim, Kang-Yoon Lee p. [1-7]

(A) proposal of methodologies for implementing digital chips in the latest processes Hye-Seung Sun, In-Shin Cho p. [1-7]

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권호기사 목록 테이블로 기사명, 저자명, 페이지, 원문, 기사목차 순으로 되어있습니다.
기사명 저자명 페이지 원문 기사목차