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Title Page

Contents

Abstract 11

Chapter 1. General Introduction 15

References 21

Chapter 2. Enhanced Doherty Power Amplifiers for High-Power Applications 25

2.1. Motivation 25

2.2. Current Optimization for Two-Stage Doherty Power Amplifier 29

2.2.1. Two-Stage Doherty Power Amplifier Model 29

2.2.2. Calculation with Practical Considerations 34

2.2.3. Two-Stage Doherty Power Amplifier with an Optimized Current 38

2.2.4. Implementation and Experimental Results 45

2.3. Dual Internally Matched FETs for Compact Doherty Power Amplifiers 51

2.3.1. Load-Pull and Source-Pull Simulation 51

2.3.2. Pre-Matching Network 55

2.3.3. Implementation and Experimental Results 59

2.4. Summary 65

References 67

Chapter 3. Highly Efficient Doherty Power Amplifier Integrated Circuits 73

3.1. Motivation 73

3.2. Compact Load Network for Doherty Power Amplifier 79

3.2.1. Transmission Line Using Lumped Components 79

3.2.2. Configuration of the Load Network 80

3.2.3. Design and Simulation Results 84

3.2.4. Implementation and Experimental Results 88

3.3. Fully Integrated Doherty Power Amplifier Based on Compact Load Network 93

3.3.1. Gate Width Optimization 93

3.3.2. Compact Load Network 98

3.3.3. Input Network for Second-Harmonic 103

3.3.4. Implementation and Experimental Results 108

3.4. Summary 115

References 117

Chapter 4. Conclusions 122

논문요약 125

List of Tables

Table 2.1. Extracted parameter values for the selected cases 36

Table 2.2. Bias conditions for the three selected cases 41

Table 2.3. Performance comparison of this study and previous studies 50

Table 3.1. Performance comparison between silicon LDMOS and GaN-HEMT 76

Table 3.2. Calculated value of each lumped component 84

Table 3.3. Performance comparison with the previously reported GaN-HEMT Doherty... 92

Table 3.4. Performance comparison to the previous GaN-HEMT Doherty PA ICs 114

List of Figures

Figure 1.1. Prediction of change for wireless communication: (a) global... 16

Figure 1.2. The operation of the ideal conventional Doherty PA: (a) load line for... 18

Figure 2.1. Doherty PA model for two-stage configuration. 29

Figure 2.2. Fundamental current of the first stage of the peaking amplifier with... 31

Figure 2.3. Calculated Doherty PA characteristics using the two-stage current... 37

Figure 2.4. Schematic of the proposed two-stage Doherty PA with optimized... 39

Figure 2.5. Simulated gains of the peaking amplifier for the three selected cases 42

Figure 2.6. Simulated results: (a) normalized fundamental currents, (b)... 44

Figure 2.7. Implemented two-stage Doherty PA. 45

Figure 2.8. Simulated and experimental results of the implemented Doherty PA... 46

Figure 2.9. Measured DEs for each peaking bias condition under the ACLR of... 48

Figure 2.10. Experimental results of the implemented Doherty PA for the three... 49

Figure 2.11. Simulated load-pull contours for efficiency and output power: (a)... 52

Figure 2.12. Simulated source-pull contours for efficiency and output power 54

Figure 2.13. Proposed pre-matching networks using MOS capacitors and bond-... 55

Figure 2.14. Impedance matching trajectories using from the proposed pre-matching... 57

Figure 2.15. Schematic diagram of the Doherty PA module using the proposed... 59

Figure 2.16. Photographs of the implemented dual IMFETs: (a) with the pre-... 60

Figure 2.17. Fabricated Doherty PA module using the dual IMFETs. 62

Figure 2.18. Measured performances for the implemented Doherty PA using the... 63

Figure 3.1. Classification of the base station transmitter according to the... 74

Figure 3.2. A cross-sectional view of the commercial GaN-HEMT process and... 76

Figure 3.3. π-type TLs using lumped components: (a) low-pass, (b) high-... 79

Figure 3.4. Schematic of the proposed load network for Doherty PA: (a) original... 81

Figure 3.5. Schematic diagram of the Doherty PA including the proposed load... 85

Figure 3.6. Simulated results for the carrier amplifier for the high -power and... 86

Figure 3.7. Simulated load impedance modulation characteristics. 87

Figure 3.8. Photographs of the implemented GaN-HEMT Doherty PA IC: (a) IC... 89

Figure 3.9. Measured performances for the 2.6 ㎓ CW signal. 90

Figure 3.10. Measured performances for the LTE signal: (a) power gain and... 91

Figure 3.11. Load network for Doherty PA ICs: (a) conventional structure, (b)... 94

Figure 3.12. Load-pull simulation setup for the gate width optimization. 95

Figure 3.13. Output power and optimum load resistance according to the gate... 97

Figure 3.14. Simulated performances for the total gate width of 2,160 ㎛. 97

Figure 3.15. Proposed load network of the Doherty PA IC: (a) original, (b) after... 99

Figure 3.16. Simulated parasitic resistances and quality factors for a spiral... 102

Figure 3.17. Load impedance modulation characteristics for the proposed load... 102

Figure 3.18. (a) Efficiency contours for the second-harmonic source... 104

Figure 3.19. Designed input network including the input splitter, an offset TL,... 105

Figure 3.20. Overall schematic diagram of the proposed Doherty PA IC. 108

Figure 3.21. 3D view of the QFN package and bond -wires for EM field... 108

Figure 3.22. Photographs of the implemented GaN-HEMT Doherty PA IC: (a)... 110

Figure 3.23. Simulated and measured power gains and DEs for the 2.6 ㎓ CW... 111

Figure 3.24. Measured performances for the downlink LTE signal: (a) power... 112

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