| 1 |
A second-order semidigital clock recovery circuit based on injection locking  |
미소장 |
| 2 |
A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os  |
미소장 |
| 3 |
Adaptive supply serial links with sub-1-V operation and per-pin clock recovery  |
미소장 |
| 4 |
A variable-frequency parallel I/O interface with adaptive power-supply regulation  |
미소장 |
| 5 |
A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability  |
미소장 |
| 6 |
A Wide-Tracking Range Clock and Data Recovery Circuit  |
미소장 |
| 7 |
A semidigital dual delay-locked loop  |
미소장 |
| 8 |
S. Y. Lee, H. R. Lee, Y. H. Kwak, B. J. Yoo, D. Shim, C. Kim, and D. K. Jeong, “250 Mbps.5 Gbps wide-range CDR with digital vernier phase shifting and dual mode control in 0.13 m CMOS,” in Proc. IEEE Asian Solid-State Circuits Conf., 2010, pp. 185.188. |
미소장 |
| 9 |
A 1.0–4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control  |
미소장 |