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Contents

A Return-to-zero DAC with Tri-state Switching Scheme for Multiple Nyquist Operations / Jaecheol Yun ; Yun-Hwan Jung ; Taegeun Yoo ; Yohan Hong ; Ju Eon Kim ; Dong-Hyun Yoon ; Sung-Min Lee ; Youngkwon Jo ; Yong Sin Kim ; Kwang-Hyun Baek 1

Abstract 1

I. INTRODUCTION 1

II. TRI-STATE SWITCHING SCHEME 2

III. IMPLEMENTATION 4

IV. EXPERIMENTAL RESULTS 5

V. CONCLUSIONS 7

REFERENCES 7

[저자소개] 8

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기사명 저자명 페이지 원문 목차
The Effect of Inhibitors on the Electrochemical Deposition of Copper Through-silicon Via and its CMP Process Optimization Paul-Chang Lin, Jin-Hai Xu, Hong-Liang Lu, David Wei Zhang, Pei Li pp.319-325

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A Switched VCO-based CMOS UWB Transmitter for 3-5 GHz Radar and Communication Systems Woon-Sung Choi, Myung-Chul Park, Hyuk-Jun Oh, Yun-Seong Eo pp.326-332

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Energy-efficient Reconfigurable FEC Processor for Multi-standard Wireless Communication Systems Meng Li, Liesbet Van der Perre, Wim van Thillo, Youngjoo Lee pp.333-340

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A High Data Rate, High Output Power 60 GHz OOK Modulator in 90 nm CMOS Chul Woo Byeon, Chul Soon Park pp.341-346

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STT-MRAM Read-circuit with Improved Offset Cancellation Dong-Gi Lee, Sang-Gyu Park pp.347-353

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Analysis of Electrical Characteristics of AlGaN/GaN on Si Large SBD by Changing Structure Hyun-Soo Lee, Dong Yun Jung, Youngrak Park, Hyun-Gyu Jang, Hyung-Seok Lee, Chi-Hoon Jun, Junbo Park, Jae Kyoung Mun, Sang-Ouk Ryu, Sang Choon Ko, Eun Soo Nam pp.354-362

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Widely Tunable Adaptive Resolution-controlled Read-sensing Reference Current Generation for Reliable PRAM Data Read at Scaled Technologies Mu-hui Park, Bai-Sun Kong pp.363-369

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A Simple Static Noise Margin Model of MOS CML Gate in CMOS Processes Hocheol Jeong, Jaehyun Kang, Kang-Yoon Lee, Minjae Lee pp.370-377

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A Return-to-zero DAC with Tri-state Switching Scheme for Multiple Nyquist Operations Jaecheol Yun, Yun-Hwan Jung, Taegeun Yoo, Yohan Hong, Ju Eon Kim, Dong-Hyun Yoon, Sung-Min Lee, Youngkwon Jo, Yong Sin Kim, Kwang-Hyun Baek pp.378-386

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Mismatch-tolerant Capacitor Array Structure for Junction-splitting SAR Analog-to-digital Conversion Youngjoo Lee, Taehyoun Oh, In-Cheol Park pp.387-400

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Structure Optimization of ESD Diodes for Input Protection of CMOS RF ICs Jin-Young Choi pp.401-410

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0.11-2.5 GHz All-digital DLL for Mobile Memory Interface with Phase Sampling Window Adaptation to Reduce Jitter Accumulation Joo-Hyung Chae, Mino Kim, Gi-Moon Hong, Jihwan Park, Hyeongjun Ko, Woo-Yeol Shin, Hankyu Chi, Deog-Kyoon Jeong, Suhwan Kim pp.411-424

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Efficient Design and Performance Analysis of a Hardware Right-shift Binary Modular Inversion Algorithm in GF(p) Piljoo Choi, Mun-Kyu Lee, Jeong-Taek Kong, Dong Kyue Kim pp.425-437

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A Low-power High-resolution Band-pass Sigma-delta ADC for Accelerometer Applications Cao Tianlin, Han Yan, Zhang Shifeng, Ray C.C. Cheung, Chen Yaya pp.438-445

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Fine-scalable SPIHT Hardware Design for Frame Memory Compression in Video Codec Sunwoong Kim, Ji Hun Jang, Hyuk-Jae Lee, Chae Eun Rhee pp.446-457

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Variation-tolerant Non-volatile Ternary Content Addressable Memory with Magnetic Tunnel Junction Dooho Choi, Kyungmin Kim, Changsik Yoo pp.458-464

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Enabling Energy Efficient Image Encryption using Approximate Memoization Seongmin Hong, Jaehyung Im, S.M. Mazharul Islam, Jaehee You, Yongjun Park pp.465-472

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A Memory-efficient Hand Segmentation Architecture for Hand Gesture Recognition in Low-power Mobile Devices Sungpill Choi, Seongwook Park, Hoi-Jun Yoo pp.473-482

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참고문헌 (13건) : 자료제공( 네이버학술정보 )

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번호 참고문헌 국회도서관 소장유무
1 A. R. Bugeja, et al, “A 14-b, 100-MS/s CMOS DAC Designed for Spectral Performance,” Solid-States, IEEE Journal of, Vol. 34, No. 2, pp. 1719-1732, Feb., 1999. 미소장
2 Q. Huang, et al, “A 200MS/s 14b 97mW DAC in 0.18um CMOS,” Solid-State Circuits Conference, 2004. ISSCC 2004. Digest of Technical Papers. IEEE International, pp. 364-365, Feb., 2004. 미소장
3 B. Schafferer, et al, “A 3V CMOS 400mW 14b 1.4GS/s DAC for Multi-Carrier Applications,”Solid-State Circuits Conference, 2004. ISSCC 2004. Digest of Technical Papers. IEEE International, pp. 360-361, Feb., 2004. 미소장
4 G. Engel, et al, “A 14b 3/6GHz Current-Steering RF DAC in 0.18um CMOS with 66dB ACLR at 2.9GHz,” Solid-State Circuits Conference, 2004. ISSCC 2004. Digest of Technical Papers. IEEE International, pp. 458-459, Feb., 2012. 미소장
5 M. J. Choe, et al, “A 1.6-GS/s 12-bit Return-to-Zero GaAs RF DAC for Multiple Nyquist Operation,” Solid-States, IEEE Journal of, Vol. 40, No. 12, pp. 2456-2468, Dec., 2005. 미소장
6 B. Jewett B, ”A 1.2GS/s 15b DAC for Precision Signal Generation,” Solid-State Circuits Conference, 2005. ISSCC 2005. Digest of Technical Papers. IEEE International, pp. 110-111, Feb., 2005. 미소장
7 W. H. Tseng, et al, “A 12-Bit 1.25-GS/s DAC in 90nm CMOS with > 70dB SFDR up to 500MHz,”Solid-States, IEEE Journal of, Vol. 46, No. 12, pp. 2845-2856, Dec., 2011. 미소장
8 IEEE Transactions on Antennas and Propagation information for authors 네이버 미소장
9 A. V. D. Bosch, et al, “A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter,”Solid-States, IEEE Journal of, Vol. 36, No. 3, pp. 315-324, Mar., 2001. 미소장
10 W. T. Lin, et al, “A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection,” Solid-States, IEEE Journal of, Vol. 47, No. 2, pp. 444-453, Feb., 2012. 미소장
11 IEEE Transactions on Antennas and Propagation information for authors 네이버 미소장
12 IEEE Transactions on Antennas and Propagation information for authors 네이버 미소장
13 A. V. D. Bosch, et al, Analog Circuit Design:Scalable Analog Circuit Design, High-Speed D/A Converters, RF Power Amplifiers, MA: Kluwer, 2002, pp. 189-201. 미소장

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