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Simulated fault injection (SFI) is widely used to assess the effectiveness of fault tolerance mechanisms in safety-critical embedded systems (SCESs) because of its advantages such as controllability and observability. However, the long test time of SFI due to the large number of test cases and the complex simulation models of modern SCESs has been identified as a limiting factor. We present a method that can accelerate an SFI tool using a checkpoint forwarding (CF) technique. To evaluate the performance of CF-based SFI (CF-SFI), we have developed a CF mechanism using Verilog fault-injection tools and two systems under test (SUT): a single-core-based co-simulation model and a triple modular redundant co-simulation model. Both systems use the Verilog simulation model of the OpenRISC 1200 processor and can execute the embedded benchmarks from MiBench. We investigate the effectiveness of the CF mechanism and evaluate the two SUTs by measuring the test time as well as the failure rates. Compared to the SFI with no CF mechanism, the proposed CF-SFI approach reduces the test time of the two SUTs by 29%–45%.

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기사명 저자명 페이지 원문 목차
Acceleration of Simulated Fault Injection Using a Checkpoint Forwarding Technique Jongwhoa Na, Dongwoo Lee pp.605-613
16-QAM OFDM-Based K-Band LoS MIMO Communication System with Alignment Mismatch Compensation Bong-Su Kim, Kwang-Seon Kim, Min-Soo Kang, Woo-Jin Byun, Myung-Sun Song, Hyung Chul Park pp.535-545
Space-Time Warp Curve for Synthesizing Multi-character Motions Mankyu Sung, Gyu Sang Choi pp.493-501
Impact of Cooperative R&D Projects on ICT-Based Technology Convergence Heongu Lee, Pang Ryong Kim, Hangjung Zo pp.467-479
Low-Power and Low-Hardware Bit-Parallel Polynomial Basis Systolic Multiplier over GF(2ᵐ) for Irreducible Polynomials Sudha Ellison Mathe, Lakshmi Boppana pp.570-581
Extensible Hierarchical Method of Detecting Interactive Actions for Video Understanding Jinyoung Moon, Junho Jin, Yongjin Kwon, Kyuchang Kang, Jongyoul Park, Kyoung Park pp.502-513
Wire Optimization and Delay Reduction for High-Performance on-Chip Interconnection in GALS Systems Myeong-Hoon Oh, Young Woo Kim, Hag Young Kim, Young-Kyun Kim, Jin-Sung Kim pp.582-591
Sentence-Chain Based Seq2seq Model for Corpus Expansion Euisok Chung, Jeon Gue Park pp.455-466
Complex Quadrature Spatial Modulation Manar Mohaisen, Saetbyeol Lee pp.514-524
Network Intrusion Detection Based on Directed Acyclic Graph and Belief Rule Base Bang-Cheng Zhang, Guan-Yu Hu, Zhi-Jie Zhou, You-Min Zhang, Pei-Li Qiao, Lei-Lei Chang pp.592-604
Dynamic Resource Allocation of Random Access for MTC Devices Sung-Hyung Lee, So-Yi Jung, Jae-Hyun Kim pp.546-557
Distortion Compensation of Reconstructed Hologram Image in Digital Holographic Display Based on Viewing Window Minsik Park, Hyun-Eui Kim, Hyon-Gon Choo, Jinwoong Kim, Cheong Hee Park pp.480-492
Non-preemptive Queueing Model of Spectrum Handoff Scheme Based on Prioritized Data Traffic in Cognitive Wireless Networks Muhammed Enes Bayrakdar, Ali Çalhan pp.558-569
Fine-Grained Mobile Application Clustering Model Using Retrofitted Document Embedding Yeo-Chan Yoon, Junwoo Lee, So-Young Park, Changki Lee pp.443-454
Separating VNF and Network Control for Hardware-Acceleration of SDN/NFV Architecture Tong Duan, Julong Lan, Yuxiang Hu, Penghao Sun pp.525-534

참고문헌 (36건) : 자료제공( 네이버학술정보 )

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번호 참고문헌 국회도서관 소장유무
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20 A Novel Simulation Fault Injection Method for Dependability Analysis 네이버 미소장
21 Simulated Fault Injection Using Simulator Modification Technique 소장
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28 R. Barbosa et al., “Assembly-Level Pre-injection Analysis for Improving Fault Injection Efficiency,” Int. Conf. Eur. Dependable Comput., Budapest, Hungary, Apr. 20–22, 2005, pp. 246–262. 미소장
29 J. Grinschgl et al., “Efficient Fault Emulation based on Post-injection Fault Effect Analysis (PIFEA),” Int. Midwest Sypm. Conf. Circuits Syst., Boise, ID, USA, Aug. 5–8, 2012, pp. 526–529. 미소장
30 Relyzer: Application Resiliency Analyzer for Transient Faults 네이버 미소장
31 B. Dӧbel et al., “Investigating the Limitations of PVF for Realistic Program Vulnerability Assessment,” Int. Conf. HiPEAC Workshop Des. Rel., Berlin, Germany, Jan. 21–23, 2013. 미소장
32 J. Li and Q. Tan, “SmartInjector: Exploiting Intelligent Fault Injection for SDC Rate Analysis,” IEEE Int. Symp. Defect Fault Tolerance VLSI Nanotechnol. Syst., New York, USA, Oct. 2–4, 2013, pp. 236–242. 미소장
33 C. Hesscot et al., “A Methodology for Stochastic Fault Simulation in VLSI Processor Architectures,”Semiconductor Research Corporation, June 2010. 미소장
34 C. Artho et al., “Using Checkpointing and Virtualization for Fault Injection,” Int. Symp. Comput. Netw., Shizuoka, Japan, Dec. 10–12, 2015, pp. 347–372. 미소장
35 H. Schirmeier, L. Rademacher, and O. Spinczyk, “Smart-Hopping: Highly Efficient ISA-Level Fault Injection on Real Hardware,” IEEE Eur. Test Sym., Paderborn, Germany, May 26–30, 2014, pp. 1–6. 미소장
36 K. Parasyris et al., “GemFI: A Fault Injection Tool for Studying the Behavior of Applications on Unreliable Substrates,” Int. Conf. Dependable Syst. Netw., Atlanta, GA, USA, June 23–26, 2014, pp. 622–629. 미소장

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