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Contents 1

(A) 1.03MOPS/W lattice-based post-quantum cryptography processor for IoT devices / ByungJun Kim ; Han-Gyeol Mun ; Shinwoong Kim ; JongMin Lee ; Jae-yoon Sim 1

Abstract 1

I. INTRODUCTION 1

II. ARCHITECTURE 2

III. SAMPLER 2

1. Real-time Psuedo Random Number Generator 2

2. Sampling Filters 2

3. Evaluation 3

IV. ARITHMETIC LOGIC ELEMENT ARRAY 3

1. Modular Multiplier 3

2. Clock Gating 5

VI. IMPLEMENTATION 5

V. CONCLUSIONS 5

REFERENCES 6

[저자소개] 6

권호기사

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기사명 저자명 페이지 원문 목차
Surface stoichiometry dependence of ambipolar SiGe tunnel field-effect transistors and its effect on the transient performance improvement Minjeong Ryu, Woo Young Choi p. 1-7

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Provisioning CSD-based storage systems with erasure-coding offloaded to the CSD Hongsu Byun, Safdar Jamil, Junghyun Ryu, Sungyong Park, Myungcheol Lee, Sung-Soon Park, Youngjae Kim p. 8-17

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Interfacial trap-based 1-row hammer analysis of BCAT and nitride layer BCAT structures in dynamic random access memory Chang Young Lim, Yeon Seok Kim, Min-Woo Kwon p. 18-24

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Improved performance of normally-off GaN-based MIS-HEMTs with recessed-gate and ultrathin regrown AlGaN barrier Shogo Maeda, Shinsaku Kawabata, Itsuki Nagase, Ali Baratov, Masaki Ishiguro, Toi Nezu, Takahiro Igarashi, Kishi Sekiyama, Suguru Terai, Keito Shinohara, Melvin John F. Empizo, Nobuhiko Sarukura, Masaaki Kuzuhara, Akio Yamamoto, Joel T. Asubar p. 25-32

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Analysis of high temperature characteristics of double gate feedback field effect transistor Myeongho Park, Kichan Kim, Seungyeon Oh, Il Hwan Cho p. 33-40

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(A) high power supply rejection and fast-transient LDO with feed-forward compensation using current sensing technique Bongsu Kim, Seung-Myeong Yu, Jongchan An, Gwangmyeong An, Junyoung Song p. 41-46

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(A) more practical indicator of MAC operational power efficiency inside memory-based synapse array Seongjae Cho, Sung-Tae Lee, Soomin Kim, Hyungcheol Shin p. 47-54

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(A) 1.03MOPS/W lattice-based post-quantum cryptography processor for IoT devices ByungJun Kim, Han-Gyeol Mun, Shinwoong Kim, JongMin Lee, Jae-yoon Sim p. 55-61

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참고문헌 (6건) : 자료제공( 네이버학술정보 )

참고문헌 목록에 대한 테이블로 번호, 참고문헌, 국회도서관 소장유무로 구성되어 있습니다.
번호 참고문헌 국회도서관 소장유무
1 J. Park, et al., “A Fully Integrated Cryo-CMOS SoC for Qubit Control in Quantum Computers Capable of State Manipulation, Readout and High-Speed Gate Pulsing of Spin Qubits in Intel 22nm FFL FinFET Technology,” ISSCC, pp. 208-209, Feb. 2021. 미소장
2 National Institute of Standards and Technology (NIST), “Module-Lattice-Based Key-Encapsulation Mechanism Standard,” Federal Information Processing Standards Publications (FIPS PUBS)203, Aug. 2023. 미소장
3 L. Ma, X. Wu and G. Bai, "Parallel polynomial multiplication optimized scheme for CRYSTALSKYBER Post-Quantum Cryptosystem based on FPGA," 2021 International Conference on Communications, Information System and Computer Engineering (CISCE), Beijing, China, 2021, pp. 361-365. 미소장
4 U. Banerjee, A. Pathak, and A. P. Chandrakasan, “An Energy-Efficient Configurable Lattice Cryptography Processor for the Quantum-Secure Internet of Things,” ISSCC, pp. 46-47, Feb. 2019. 미소장
5 G. Xin, et al., “VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture,” TCAS-I, vol. 67, no. 8, pp. 2672-2684, Aug. 2020. 미소장
6 Y. Zhu, et al., “A 28nm 48KOPS 3.4μJ/Op Agile Crypto-Processor for Post-Quantum Cryptography on Multi-Mathematical Problems,” ISSCC, pp. 514-516, 2022. 미소장

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